AM623: DFS peripheral impact made by cpufreq and latency implications for the clocks

Hi Blake,

Blake Carpenter said:

I cannot figure out what TI-CPUFREQ actually changes.

CPUFreq simply allows the processor to adjust the frequency of the A53 cores dynamically from a Linux application. CPUFreq will only control the clocking of the application's core which means the application running on the A53 can control the speed the A53 runs at.

At a register level, CPUFreq will change the clock divider register value. For example when scaling down the A53 speed from 800MHz to 400MHz, the PLL speed (2400MHz) remains the same but it will be divided by 6 instead of 3 before feeding into both A53 cores.

Blake Carpenter said:

I suspect the LPDDR4 speed will change?,

CPUFreq does not control anything else including peripherals, DDR and others.

Changing the A53 core speed will not impact the functionality of the other peripherals. The A53 cores use a different PLL and divider than peripherals.

Blake Carpenter said:

For the CPU, from the TRM AM62 figure 6-40, I am assuming a new frequency will be called for then there will be a latency for PLL lock then some margin added.  Is there other factors at play?

Can you clarify what you mean? Its safe to assume that writing to a PLL register will have some latency until A53 actually responds to the changes.

Blake Carpenter said:

Let’s say we change the CPU frequency from ‘2X’ to ‘1X’. Is there some recalibration of the clocks that is automatically done in Linux for the different peripherals (AHB, APB, DDR ctlr, SPI, timers, etc.)? I am trying to assess any unintended consequences that may be seen on different modules and/or peripherals when we change the CPU frequency.  

I don't fully understand this query.

I recommend you look at the AM62x Clock Tree Tool: https://dev.ti.com/sysconfig/?product=CLOCKTREE-AM6X&device=AM62x

This is for AM62x since the AM62L version is still in development. This tool will explain the clocking architecture of the device.

Notice that PLL8 is only used by the A53 cores.

There are other peripherals that source multiple clocks (like MCASP for example) but they will be completely unaffected by A53 speed changes.

Blake Carpenter said:

Can you walk me through the steps for cpufreq to make the change to a new processor operating speed?

Take a look at the Linux SDK documentation for how to use CPUFreq: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/Power_Management/pm_dfs.html

Blake Carpenter said:

I am assuming you can manually gate a core off if you want its power consumption to be at the lowest level?

Yes this will be possible by putting the second A53 into a WFI state (waiting for interrupt).

Best Regards,

Anshu