Hello,
We are currently evaluating our next GEN devices to be using homogenous multi core DSP SOC and devices. We have used in the past Heterogenous systems like the DaVinci SOCs. An impairment to time to market where we have sunk a lot of engineering time has been the IPC mechanisms in an heterogenous environment.
Ti has made significant progress in that area offering tools and packages like the MCSDK, however thse approaches still leave to the programmer the tedious and complicated software issues of managing multiple RTOS instances and managing caching between multiple cores and tasks running on those cores.
Even though the MCSDK and other mechanism like DSPLink have addressed certain cache-coherency issues, they do it a large execution/performance cost which we always had to address by developing a more bare-metal approach to IPC shared memory channels.
All of this could become a lot simpler if:
1) Ti current and future SOC multi core DSP would provide cache-coherency help in Hardware across cores ?
2) SYS/BIOS 7.0 ? would introduce true SMP (Symmetric Multiprocessing) support in the future so a single instance of SYS/BIOS runs on a particular SOC, and the RTOS/HW take care of the details of IPC, cache-coherency and Core load for the application ?
Hense my questions, is MCSDK the first baby strep towards an SMP SYS/BIOS in the future and will Ti provide additional HW help in its multicore DSP design to faciliate this ?
Regards,
