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DSP/BIOS 5 vs SYS/BIOS 6 and DSPLink version suggestions?

Judson Wilson
Intellectual 620 points
Other Parts Discussed in Thread: OMAP-L138

I have played around with both versions a little bit, and have read various docs and wikis.

SYS/BIOS 6 appears to be very feature rich, however when I look at the code size benchmarks it appears that the code size bloat has been on an exponential path for every subrevision.  This worries me because I have a system that needs to fire HWI's on the order of 15-30khz, with a few kilobytes of "static" code that runs every HWI, and other code that will not be so static. Due to caching concerns, it seems like I should cut the L1P cache in half, and put some HWI, kernel, and the HWI-called function in the L1P SRAM.  That makes me think that DSP/BIOS 5 is probably a more solid bet, based on size.

I'd like to start with the highest probability bet on which version to use. A suggestion on that would be helpful.

Also, it appears the latest version of DSP/BIOS is not compatible with BIOS 5.4x ?   Is this true?

Finally I am looking for a bit of advice on how to benchmark a HWI, especially in the context of a cached system.  It is easy enough turn the cache on/off, and use the clock to measure the body of an HWI implmentation, but figuring out how to see how long the BIOS code for the HWI firing code takes, and which parts of BIOS that would be best to put into the SRAM is starting to get a little beyond me.  Or maybe it doesn't really matter if my HWI triggered code is on the order of a few thousand clock cycles?

Tips appriciated!

Thanks

  • 0
    TI__Genius 17205 points

    What device are you on?  That may limit your options.

    DSP Link supports BIOS 5, SysLink supports BIOS 6 - that may also constrain things.

    Chris

  • 0 in reply to Chris Ring
    Intellectual 620 points

    OMAP-L138, probably running near 440Mhz.

    Sorry, I originally had it in the title but removed it.

     

    I didn't even realize there were two different LINK products for DSP/BIOS and SYS/BIOS.

  • 0 in reply to Judson Wilson
    Intellectual 620 points

    I should probably add that I am not extremely concerned with latency, but I am concern with the overall amount of time spent processing the HWIs.  A significant increase in the execution time of my HWIs (again, think on the order of 3000 processor clock cycles) can cause the HWIs to overlap (which would be bad, in my case), or chew up a significant portion of my processing time as a whole.

    This is a realtime system where a failure to meet the schedule is 100% not acceptable. There will be lots of threads of various priority, but the HWI (or maybe SWI, not sure that it matters) level concerns me the most because it happens so often and is so computation heavy. Also, it is not a tight loop like a 15 element FIR, RATHER it is 2k of code and several arrays of 32bit and 64bit fixed point data.