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TDA4VH-Q1: 1.8V supplies

SH
Intellectual 400 points
Part Number: TDA4VH-Q1


Tool/software:

Since according to the Combined MCU and Main Domains Power Up Sequencing the 1.8V voltages start ramp at the same time (at T1), what would be the reason why in PDN-3F power Connections the VDDA_MCU 1.8V is supplied from a PMIC LDO4 and VDD_MCUIO_1 is supplied from LDO1 and not from PMIC Buck4 that is already powering the SoC VDD_IO 1.8V?
If VDDA_MCU, being analog supply, needs to be supplied from LDO4, does VDD_MCUIO have some similar (noise) requirements?

Also, regarding the PDN-3F, what would be the reasons to supply 1.8V VDDA_PHY and VDDA_PLL from their own discrete LDOs? Or could they be combined together to one LDO?

  • 0
    TI__Expert 7075 points

    The answer to all your questions is that PDN-3F is an "Isolated PDN scheme". By Isolated I mean the SoC's MCU & Main input supplies are independently supplied from different power resources. This allows for "Freedom From Interference" (FFI) in case one power resource or power rail encounters an issue, both the MCU & Main processing domains will not be affected. 

    The "Grouped PDN schemes" supply SoC's MCU & Main input supplies from combined/common power resources (regulators, power rails, etc.). This approach reduces number of power resources but does not enable FFI, resulting in a single fault potentially impacting both MCU & Main processing domains concurrently.

    Isolated PDNs are defined as PDN-3A thru -3F

    Grouped PDNs are defined as PDN-3G thru -3M

  • 0 in reply to Bill McCracken
    Intellectual 400 points

    Thank you for the comments.

    Where could I find the latest information on PDN-3G thru -3M?