Tool/software:
Hi team,
We have questions about LPDDR4 ZQ training sequence by TI SoC.
ZQ calibration is one of DDR training. In general, controller need to issue a “ZQ start” command and “ZQ latch command ” command to DRAM to complete the ZQ calibration.
However, when DRAM has 2 channels, the different ZQ calibration behavior varied with different controllers. Could you help sharing how TI SoC does the ZQ calibration sequence?
For example:
1. One ZQ start with one ZQ latch commands for one channel.
2. One ZQ start with 2 consecutive ZQ latch commands (double latch) for one channel.
3. Double ZQ start with one ZQ latch command for one channel.
4. SoC trigger ZQ calibration command to both channels simultaneously or one after the other?
Thanks.
Maurice
