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TMS320DM368 - DMVA2 GPIO Interrupts

Elvis Mota
Prodigy 200 points
Other Parts Discussed in Thread: TMS320DM368

Hi,

I'm trying to find out what is the correct answer to how many GPIOs are available to be used as interrupts to the processor in both TMS320DM368 and DMVA2 devices.

The document SPRUFH8C - Revised January 2011 General-Purpose Input/Output (GPIO) states on its first page under section 1.2 Features, and I quote, "All GPIO signals can be used as interrupt sources with configurable edge detection."

Then, in Section 3 - Registers (page 18), it lists GPIO Banks 0 and 1 as being configurable for Interrupt usage (there is only one set of offset addresses, though). However, the GPIO Interrupt Per-Bank Enable Register (BINTEN) (page 20) only configures Banks 0 and 6.

Bank 0 is being used as EMAC interface and the PRTCSS module (Bank 6) is not wired at all in my custom application. GIO0 is being used as a PHY interrupt. The document is to say the least misleading if indeed only Banks 0 and 6 can have their respective GPIOs configured as Interrupts.

I'm trying to avoid having to design any external logic to have to deal with multiple devices requesting one single interrupt. A clear answer to this question is highly appreciated.

Also, can the interrupts for the PRTCSS module be used to handle external events even if the power management circuit and RTC is not used?

Regards,

  • 0
    TI__Genius 9510 points

     

    The GPIO USG is more generic, but specific information relating to which GPIOs are route to the ARM is described in

    http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprufg5a&fileType=pdf, section 8.

    You'll see the list of GPIO that can be used, which are outside of the bank0 and bank6 range. 

  • 0 in reply to Marcus Cooksey
    Prodigy 200 points

    Thank you for replying to my question Marcus,

    I'm however still confused by the documentation. Say that I want to use a pin whose BGA id is D17 in the DMVA2 device. This pin is labeled as GIO85/COUT0(B3)/PWM3.

    In the document you sent me a link to, it says in page 89 that Interrupt number 28 is labeled as PWM3INT or TINT9 and its source is PWM3 or Timer 4 - TINT34.

    So my question is:

    Pin D17 is in Bank 5, how do I enable this Bank and consequentely this pin to route an interrupt to the processor?

    Can you give an example how to set the GPIO Interrupt-Per-Bank Enable Register (BINTEN) to enable this interrupt?

     

    Regards,

     

    Elvis

  • 0 in reply to Elvis Mota
    TI__Expert 4510 points

    Hi Elvis,

    The statement in GPIO user guide documentation " All GPIO signals can be used as interrupt sources with configurable edge detection" as it applies to DM365 is incorrect. I apologize for this confusion caused by documentation error.

    On Dm365/DM368/DMVAx devices, interrupts are available from

    a) Bank 0 GPIO[0-15]

    b) 3 interrupts GPIO[106:104] from Bank 6 dedicated to PRTCSS subsystem.

    This information is mentioned correctly in device datasheets for example Page 87 of DM365 datasheet states this.

    Also, as you can see from Table 54, only GIO[0:15] and GPIO[106:104] shared with PWRCTRIO[2:0] are mapped to AINTC Interrupt controllers (Page 89 of ARM Subsystem Guide).

    Hope this helps.

     

    Prateek