AM69A: How to print from C7x-MMA-TIDL files?

Hi Azer, 

Could you send your changes and logs to better understand your situation? 

Thanks,

Christina

Hi,

The main issue is that my changes are not being recognized.

ti_dl files are compiled correctly according to the steps outlined in the TIDL Custom Layer documentation. (md_tidl_custom_layer.html)

However, as shown in the logs below, the modified text does not appear during compilation : 

tidl_tools_path                                 = /home/developer/edgeai/edgeai-tidl-tools/tidl_tools 
artifacts_folder                                = artefacts/artefacts_custom_layer_v0 
tidl_tensor_bits                                = 8 
debug_level                                     = 1 
num_tidl_subgraphs                              = 16 
tidl_denylist                                   = 
tidl_denylist_layer_name                        = 
tidl_denylist_layer_type                        = 
tidl_allowlist_layer_name                       = 
model_type                                      =  
tidl_calibration_accuracy_level                 = 7 
tidl_calibration_options:num_frames_calibration = 4 
tidl_calibration_options:bias_calibration_iterations = 3 
mixed_precision_factor = -1.000000 
model_group_id = 0 
power_of_2_quantization                         = 2 
ONNX QDQ Enabled                                = 0 
enable_high_resolution_optimization             = 0 
pre_batchnorm_fold                              = 1 
add_data_convert_ops                            = 0 
output_feature_16bit_names_list                 =  
m_params_16bit_names_list                       =  
m_single_core_layers_names_list                 =  
Inference mode                                  = 0 
Number of cores                                 = 1 
reserved_compile_constraints_flag               = 1601 
partial_init_during_compile                     = 0 
ti_internal_reserved_1                          = 

========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              10_00_08_00             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              10_00_02_00             |
-------------------------------------------------------------------------------

============================== [Parsing Started] ==============================

[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 2 Tflite layer type --- 17 layer output name--- PartitionedCall:0  -- [tidl_tfLiteRtImport_core.cpp, 3090]

Total Nodes = 1
-------------------------------------------------------------------------------
|          Core           |      No. of Nodes       |   Number of Subgraphs   |
-------------------------------------------------------------------------------
| C7x                     |                       1 |                       1 |
| CPU                     |                       0 |                       x |
-------------------------------------------------------------------------------
============================= [Parsing Completed] =============================

In TIDL_tfliteRtImportInit subgraph_id=1
Layer 0, subgraph id 1, name=PartitionedCall:0
Layer 1, subgraph id 1, name=serving_default_max_pooling2d_1_input:0
In TIDL_tfliteRtImportNode, TIDL Layer type - 2, Tflite builtin code type - 17 
==================== [Optimization for subgraph_1 started] ====================

In TIDL_runtimesOptimizeNet: LayerIndex = 3, dataIndex = 2 
----------------------------- Optimization Summary -----------------------------
----------------------------------------------------------------------------
|       Layer       | Nodes before optimization | Nodes after optimization |
----------------------------------------------------------------------------
| TIDL_PoolingLayer |                         1 |                        1 |
----------------------------------------------------------------------------

=================== [Optimization for subgraph_1 completed] ===================

In TIDL_runtimesPostProcessNet 
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.31s:  VX_ZONE_ERROR:Enabled
 0.39s:  VX_ZONE_WARNING:Enabled
 0.41668s:  VX_ZONE_INIT:[tivxInit:190] Initialization Done !!!
************ TIDL_subgraphRtCreate done ************ 
  0%|                                                     | 0/4 [00:00<?, ?it/s] tidl_tfLiteRtImport_delegate.cpp Invoke 526 
*******   In TIDL_subgraphRtInvoke  ******** 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 290.000000 285.000000 451.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ************ Frame index 1 : Running float inference **************** 

tidl_tfLiteRtImport_delegate.cpp Invoke 647 
tidl_tfLiteRtImport_delegate.cpp Invoke 526 
*******   In TIDL_subgraphRtInvoke  ******** 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 15.000000 144.000000 306.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ************ Frame index 2 : Running float inference **************** 

tidl_tfLiteRtImport_delegate.cpp Invoke 647 
tidl_tfLiteRtImport_delegate.cpp Invoke 526 
*******   In TIDL_subgraphRtInvoke  ******** 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 9.000000 1690.000000 307.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ************ Frame index 3 : Running float inference **************** 

tidl_tfLiteRtImport_delegate.cpp Invoke 647 
tidl_tfLiteRtImport_delegate.cpp Invoke 526 
*******   In TIDL_subgraphRtInvoke  ******** 
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     1,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 11.000000 110.000000 2829.000000 
*******  TIDL_subgraphRtInvoke done  ******** 

 ************ Frame index 4 : Running fixed point mode for calibration **************** 

In TIDL_runtimesPostProcessNet 

-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
[===================>                                                         ] [======================================>                                      ] [=========================================================>                   ] [=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [1 / 3]: ------------------
[===================>                                                         ] [======================================>                                      ] [=========================================================>                   ] [=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [2 / 3]: ------------------
[===================>                                                         ] [======================================>                                      ] [=========================================================>                   ] [=============================================================================] 100 %

------------------ Fixed-point Calibration Iteration [3 / 3]: ------------------
[===================>                                                         ] [======================================>                                      ] [=========================================================>                   ] [=============================================================================] 100 %

==================== [Quantization & Calibration Completed] ====================

========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

======================== Subgraph Compiled Successfully ========================


 Final number of subgraphs:1 , 1 nodes delegated to accelerator 

Running Runtimes GraphViz - /home/developer/edgeai/edgeai-tidl-tools/tidl_tools/tidl_graphVisualiser_runtimes.out artefacts/artefacts_custom_layer_v0/allowedNode.txt artefacts/artefacts_custom_layer_v0/tempDir/graphvizInfo.txt artefacts/artefacts_custom_layer_v0/tempDir/runtimes_visualization.svg 
tidl_tfLiteRtImport_delegate.cpp Invoke 647 
100%|█████████████████████████████████████████████| 4/4 [00:02<00:00,  1.95it/s]
************ in TIDL_subgraphRtDelete ************ 
 MEM: Deinit ... !!!
MEM: Alloc's: 26 alloc's of 48218781 bytes 
MEM: Free's : 26 free's  of 48218781 bytes 
MEM: Open's : 0 allocs  of 0 bytes 

I have added printf or TI print functions (such as TIDL_GLOBAL_REPORT_INFO) in files located in the custom or utils folders of ti_dl, but nothing is displayed.

To compile, I use the TIDL_TOOL_PATH provided by edgeai_tidl_tool. However, some libraries of tidl_tool are recompiled during the custom layer process. I tried modifying the TIDL_TOOL_PATH to RTOS_SDK_PATH/c7x-mma-tidl/tidl_tool, but this results in a segmentation fault.

Could you please advise on the correct path for TIDL_TOOLS_PATH so that I no longer encounter segmentation faults and my changes in the custom folder are properly integrated?

And then, could you tell me how to print in ti_dl files so I can debug custom layer.

Thanks and regards,

Azer

Hi Azer,

Setting the TIDL_TOOLS_PATH is documented https://github.com/TexasInstruments/edgeai-tidl-tools/tree/master/examples/osrt_python and https://github.com/TexasInstruments/edgeai-tidl-tools/blob/master/docs/advanced_setup.md  It should be set to where the .so shared libraries are on your system.  Why the segmentation fault occurs depends on your setup.  It could be that the output directory is not writable or your .so are not for the correct ISA (you are using ARM .so and trying to link an x86 binary), or a bunch of other reasons.  It may not by TIDL_TOOLS_PATH at all.  This is something you have to debug in your setup and send us a bit more information before we can make a determination of cause.

Also, we try to keep E2E threads focused on one topic.  This thread appears to be multiple topics; the title is the print, not the build problem.  

Regards,

Chris

Hi,

Christina Kuruvilla said:

Could you send your changes and logs to better understand your situation? 

In my previous answer, you can see two C7x-MMA-TIDL files with my changes (printf additions) as requested.

Then, the requested logs are those of the compilation. The compilation uses one of the files modified above, so it seems abnormal to me that I don't see these changes in the compilation logs.

To supplement my last answer, I provided a research lead by modifying the TIDL_TOOL_PATH because perhaps the libraries used for the compilation aren't the ones that take my changes into account. From your answer, I see that this avenue isn't viable.

So, by looking only at the files I modified and the compilation logs (see my last message), can you tell me why I don't see my changes and then how to see my prints?

Thanks and regards,

Azer

Hi Azer,

Can you try a clean build and make sure first add printf to the custom process API, and then build the custom layer library?

Warm regards,

Christina

Hi,

I did a clean build and add printf in one file from custom process API : 

Then I did build the custom layer library. You can find all the logs from the build  : tidlModelImport, C7x-mma-tidl and in sdk_builder.

The compilation logs are still the same. Do you have any idea ?

Thanks,

Azer

4212.logs.zip

Hi Azer,

Unfortunately, I am not sure why this occurs. Please give me some time to investigate and I will get back to you.

Thanks,

Christina