AM625SIP: PCB layer and OTP burning

Hello Jack, 

Thank you for the query.

Jack said:

Is there a reference from another customer that is designed with 4 layers?

The below document could provide you with the number of layers that may be required. 

AM62x SiP Escape Routing for PCB Design

https://www.ti.com/lit/an/spradd4/spradd4.pdf

Jack said:

-Is it possible to do OTP burning (HSM related) with AM625SIP?

https://www.ti.com/lit/ds/symlink/am625sip.pdf

8.1.2 Device Naming Convention

Jack said:

Is it true that AM62SIP-EVM is designed for 10 layers?

The number of layer are higher due to design reuse.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1357533/faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-schematics

Regards,

Sreenivasa

Hello Jack, 

The AM625SIP can be escaped in 4 layers. Feasibility study proving that 100% escapability could be achieved with 4 layers has been done.

We may not have any design files to support the study.

Regards,

Sreenivasa