PROCESSOR-SDK-AM62X: M4 Watchdog

Hello Steve,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Hello Steve,

Currently, we don't support the WDT on M4F in the MCU+SDK.

But, as per SOC, this is supported.

If you want to enable the WDT on the M4F core, please refer below. 

And one more thing is that the SOC can't make the Reset only the M4F core after the WDT expires and once the WDT is expires then entre SOC gets Reset .

To make the SOC Reset, users need to go with the ESM module and the FAQ below is helpful to integrate this feature into the your application .

The below link is helpful to achieve your requirements. Even if this is on other devices it is still valid for AM62X.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1362747/am6442-wdt-on-m4f

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1414222/faq-am6442-watchdog-debug-and-configuration-guide-for-all-sitara-am6x-mpu-devices

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1283237/faq-am64x-am62x-how-to-reset-the-soc-when-wdt-timer-expires-in-am64x-and-am62x

Regards,

Anil.

Thanks for the quick response Anil.

I found the first link in my search of E2E before posting my question.  It seems like that depends on having the Watchdog_ functions implemented in the library binary, which isn't the case for the M4 on the AM62x.  Or have I misunderstood the reference?

The last link looks quite promising.  But I need to take some time to digest and work through the details to see if it has all that I need.  Hopefully, with juggling, I can do that over the next few days.

Again, thanks for you help.
    Steve

Hello Steve,

Steve Schefter said:

I found the first link in my search of E2E before posting my question.  It seems like that depends on having the Watchdog_ functions implemented in the library binary, which isn't the case for the M4 on the AM62x.  Or have I misunderstood the reference?

You need to follow the same steps as in the above link.

Even these steps belong to AM64X and the same method is valid for AM62X.

Once, integrated all the steps, let me know if you face any issues.

Regards,

Anil.

Hi Anil.

In reference to the first link you said:

Swargam Anil said:

You need to follow the same steps as in the above link.

I'm not understanding that.  The first link provides code (empty.c) that calls the functions Watchdog_clear(), Watchdog_open(), Watchdog_close().  As I indicated, those functions do not exist in the M4 libraries in the AM62x MCU+ SDK.  How can I follow the steps in that link?

With reference to the third link:

Am I correct to understand that since there is an Interrupt ID for WKUP_RTI0_INTR_WWD_0 in ESM0_INTERRUPT_MAP and not in WKUP_ESM0_INTERRUPT_MAP, that it is only possible to enable a system reset via an M4 watchdog expiry from a custom R5 firmware binary and not via the M4 firmware itself?

Thanks,
    Steve

Hello Steve,

The Watchdog_clear, open and close APIs are there in the MCU+SDK drivers .

Now, we need to compile for M4F core drivers.

Please integrate make file changes and driver.h files from the comment below in Link1.

Later, compile the driver and application. 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1362747/am6442-wdt-on-m4f

My suggestion is that instead of integrating the above changes already available the WDT in the SDL component.

Please use the SDL M4F example and integrate it into your application and, along with it, enable the SOC Reset setting with the help of the MCU_CTRL_MMR register rather than the MAIN_CTRL_MMR register.

Try these steps and let me know whether the SOC is reset or not after the WDT expires.

C:\ti\mcu_plus_sdk_am62x_10_00_00_14\examples\sdl\rti\UC1\am62x-sk\m4fss0-0_nortos

Regards,

Anil.