AM6442: Ethernet Port Enablement Packet Priority

Hello Mari, 

Mari Tsunoda said:

They were looking at the sample provided here: https://software-dl.ti.com/processor-industrial-sw/esd/ind_comms_sdk/am64x/latest/docs/api_guide_am64x/EXAMPLES_INDUSTRIAL_COMMS_ETHERNETIP_ADAPTER_TUNNELING_DEMO_HOME.html#ETHERNETIP_TUNNELING_INTRODUCTION

Let me loop in a colleague who is more familiar with this example. Please kindly ping this thread again if you don't hear a response next week.

In the meantime, another example that might be useful is https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_01_00_32/exports/docs/api_guide_am64x/EXAMPLES_ENET_INTERCORE_ICSSG.html 

-Daolin

Hi Mari Tsunoda,

Thanks for your query.

Mari Tsunoda said:

 Five Ethernet Port Enablement on AM64x and AM243x

This document will help to enable access of multiple ethernet ports parallel from A53 and R5F.

Mari Tsunoda said:

They were looking at the sample provided here: https://software-dl.ti.com/processor-industrial-sw/esd/ind_comms_sdk/am64x/latest/docs/api_guide_am64x/EXAMPLES_INDUSTRIAL_COMMS_ETHERNETIP_ADAPTER_TUNNELING_DEMO_HOME.html#ETHERNETIP_TUNNELING_INTRODUCTION

This example shows about how to use shared memory based Intercore driver for data traffic sharing coupled with ethernet driver (ICSS_EMAC) and LwIP bridge. It uses ICSS_EMAC ethernet driver underneath with LwIP TCP/IP networking stack

But,

The example demonstrates the driver feature to exchange ethernet (IEEE 802.1) packets between r5fss0-0 and a53 core (linux), via shared memory and ethernet bridge (LwIP software bridge). CPU core r5fss0-0 fully owns & configures ICSSG1 peripheral resource to handle packet reception/transmission directly from/to ICSSG1.

It steers the traffic to linux based on MAC address, using LwIP bridge.

Seperate MAC addresses are used to differentiate different CPU core traffic.

Seperate TCP/IP (LiWP) stack instances are setup in each core.

Furthermore, at application level TCP echo servers are initialized on socket port 8888, in each core to handle the TCP traffic.

Regards

Ashwani

Hi Ashwani,

Thanks for your response.

Based on your comment, my understanding is that this example is pretty similar to what they want to do. I have a few questions.

• I see that the example considers the R5F core as the main core and the Linux core as the remote core. If my customer wants to boot the R5F core after booting linux, will they have to make some changes to enable this then OR does boot order does not matter?
• Will it be possible to configure the CPSW port instead of the ICSSG1 port? If so, what changes will they have to make in the sample code other than sysconfig?
• How can packet priority be set between the Linux and R5F core?

Could you clarify what changes they should make?

Best regards,

Mari Tsunoda

Hi Mari Tsunoda ,

Allow me couple of days to sync internally on this and get back to you.

Feel free to ping back if you do not hear by next week.

Regards

Ashwani

Hi Ashwani,

Any update?

Best regards,

Mari

Mari Tsunoda said:

will they have to make some changes to enable this then OR does boot order does not matter?

Yes, they have to make changes for Linux interface. Current implementation is assuming R5F(main core) is coming up first and providing response to linux IPC communication. May be Daolin Qiu can provide more info here.

Mari Tsunoda said:

Will it be possible to configure the CPSW port instead of the ICSSG1 port?

Mari Tsunoda said:

How can packet priority be set between the Linux and R5F core?

Checking internally on this, will get back to you.

Regards

Ashwani

Hi Mari,

From what I understand, this is the implementation you are looking for - Intercore Ethernet Packet Exchange With ICSSG, Using LwIP Bridge - with CPSW (instead of ICSSG) and traffic tunneling between Linux and R5F core? Please correct me if I am wrong. 

Mari Tsunoda said:

If my customer wants to boot the R5F core after booting linux, will they have to make some changes to enable this then OR does boot order does not matter?

In the EtherNet/IP implementation you are referring to above, SPL boot flow is used and the R5F application binaries are loaded using Linux remoteproc.

Linux comes up and then the R5F application starts. Please find the boot flow here - https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/10_00_07_04/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow

Mari Tsunoda said:

Will it be possible to configure the CPSW port instead of the ICSSG1 port? If so, what changes will they have to make in the sample code other than sysconfig?

Since you will be using Linux, there will be device tree and resource configuration changes needed on the Linux side as well to transfer ownership of CPSW from Linux to R5 (the EtherNet/IP example documentation mentions the same changes for ICSSG ownership).

Apart from that, there might be some chnages needed on the MCU side as well. I will check this next week and get back to you.

Mari Tsunoda said:

How can packet priority be set between the Linux and R5F core?

Can you explain more on this? What is the objective for using packet priority?

Regards,

Nitika

Hi Nitika,

Thanks for your reply.

Nitika Verma said:

From what I understand, this is the implementation you are looking for - Intercore Ethernet Packet Exchange With ICSSG, Using LwIP Bridge - with CPSW (instead of ICSSG) and traffic tunneling between Linux and R5F core? Please correct me if I am wrong. 

Yes, you are correct.

So let me make sure I understand the difference between EtherNet/IP Adapter Intercore Tunneling example and Intercore Ethernet Packet Exchange With ICSSG, Using LwIP Bridge example (enet_intercore_icssg). 

enet_intercore_icssg:

• Uses two R5F cores and ICSSG ethernet port. The two R5F cores share data traffic using the shared memory. 
  
• Changes needed to port to customer's usecase:
  • Change R5F0_1 core to A53 core
  • Change ethernet port used from ICSSG to CPSW port.

Ethernet/IP Intercore example:

• Uses A53 and R5F core and ICSSG ethernet port. The A53 core and R5F core share data traffic using the shared memory. 
  • 
• Changes needed to port to customer's usecase:
  • Change ethernet port used from ICSSG to CPSW port.

Please correct me if my understanding is wrong.

If my understanding above is correct, it seems like the Ethernet/IP intercore example is a closer implementation to my customer's usecase and will require less changes. It also seems like the change from R5F core to A53 for the enet_intercore_icssg example will need quite a lot of effort.

Nitika Verma said:

Can you explain more on this? What is the objective for using packet priority?

• R5F will send packets at a constant interval (highest priority)
• A53 core will send TCP/UDP in between R5F transmission above

This is the only information they have given me.

Best regards,

Mari Tsunoda

Hi Mari,

Mari Tsunoda said:

Changes needed to port to customer's usecase:

• Change ethernet port used from ICSSG to CPSW port.

The EtherNet/IP example has the EtherNet/IP stack integrated in it. If the customer does not want to use Industrial protocols I do not recommend looking into that example.

The MCU+ SDK intercore tunneling example would be easier use. Enabling the macro ENET_IS_LINUX_PRESENT (by enabling Linux IPC and disabling IPC for every other core in sysconfig) is all that will be needed to use A53 Linux instead of R5F0_1.

So, we can continue with the MCU+ SDK example for the customer's use case.

Regards,

Nitika

Hi Nitika,

Thanks. I will push them towards te MCU+SDK intercore tunneling example.

Regarding packet priority, is it possible to configure for customer usecase?

Best regards,

Mari Tsunoda

Hi Mari,

Mari Tsunoda said:

• R5F will send packets at a constant interval (highest priority)
• A53 core will send TCP/UDP in between R5F transmission above

We do have ways to attach priority to incoming packets. From what I understand from here, are they looking for packet priority in the transmit path?

Regards,

Nitika

Hi Nitika,

Yes you are correct. 

Could you tell me the how to set priority for packets on both Linux and FreeRTOS?

Also, at which layer can they set priority? 

For example can they do VLAN PCP or DSCP tagging to set priority?

If there is any documentation I can point my customer to that would be great.

Best regards,

Mari Tsunoda

Hi Mari,

I am discussing on the possible ways to do this with the team, will update you in some time.

Regards,

Nitika

Hi Nitika,

Please keep me updated.

Best regards,

Mari

Hi Nitika,

Any update on this?

Best regards,

Mari Tsunoda

Hi Mari,

Apologies for the delay, I was out-of-office for a while. As per my discussion with the dev team, VLAN PCP can be used for the use case.

The R5F side implementation of VLAN along with CPSW is available in the EXAMPLES_ENET_CPSW_EST.html

Since Linux is involved here, for VLAN traffic to be sent from/received by Linux. The PCP tag can be added directly and sent. A VLAN interface will have to be created on top of the default non-VLAN tunneling interface. An example command to create a VLAN Interface is:

ip link add link eth1 name eth1.10 type vlan id 10

Assuming that eth1 is the intercore tunneling interface in Linux and VLAN 10 is being used.

Has the customer started modifying the MCU+ SDK example to use Linux? Which version of the SDK will they be using?

Regards,

Nitika

Hi Nitika,

Thanks for the response.

Nitika Verma said:

The MCU+ SDK intercore tunneling example would be easier use. Enabling the macro ENET_IS_LINUX_PRESENT (by enabling Linux IPC and disabling IPC for every other core in sysconfig) is all that will be needed to use A53 Linux instead of R5F0_1.

So, we can continue with the MCU+ SDK example for the customer's use case.

Just want to confirm, is this the only steps necessary to enable A53 linux instead of R5F core (for one of the cores)?

Also, the original IPC sample program you provided was using ISSG port instead of CPSW port. What would be the steps to change from ICSSG -> CPSW port? They tried on their own but could not get it working.

Best regards,

Mari

Hi Mari,

In the R5F0_0 (main core) example, the macro ENET_IS_LINUX_PRESENT will have to be set by enabling Linux IPC in sysconfig. This is the only major change needed here.

More changes are needed on the processor SDK side - modifying the DTS, resource allocation and other changes mentioned in the ETHERNETIP_ADAPTER_TUNNELING_DEMO.

Since the customer is using CPSW instead of ICSSG, they will have to disable the CPSW module on the Linux side instead of ICSSG.

Mari Tsunoda said:

What would be the steps to change from ICSSG -> CPSW port? They tried on their own but could not get it working.

Can you share the steps they have tried?

Using CPSW along with LwIP bridge has been implemented in our 5-port Ethernet Switch example with the below architecture:

You can find the appnote here - https://www.ti.com/lit/an/spradh8/spradh8.pdf, and the example code in Github - enet_multicore_lwip

Regards,

Nitika