[FAQ] AM62L: Custom board hardware design – OSPI0 interface implementation (on TMDS62LEVM) guidelines

Hi Board designers, 

Guidance and inputs provided by our device expert: Paul Eaves

I have listed (highlighted) some of the recommendations (expectations and limitations) board designers are required to be familiar and follow, when connecting two memory devices to the AM62Lx OSPI0 peripheral.   

OSPI0 interface

The AM62lX supports interfacing to

• X1 memory device
• X2 memory devices

Interfacing to x1 memory device

When interfacing to x1 memory device, recommend following the OSPI0 interface approach that is implemented in AM64x, AM62x, AM62Ax, AM62D-Q1 or AM62Px processor families SKs.

Interfacing to x2 memory devices

When interfacing to x2 memory devices, the recommendation is to follow the OSPI0 interface approach that is implemented in the AM62L processor family EVM.

 One of the two OSPI/QSPI memory device must provide a DQS output that is connected to the AM62Lx OSPI0_DQS input.  This memory device will use the AM62Lx OSPI0_CLK output as the clock source, and will not use the AM62Lx OSPI0_LBCLKO clock output.  The memory device will be located on the far-end of the OSPI0 data bus.  The memory device will be able to operate at high data transfer rates because it is located at the far-end of the signal traces and will not encounter signal distortion caused by reflections from stubs.

 The second OSPI/QSPI memory device will only operate in non-PHY mode (Tap SDR or Tap DDR), so the memory device does not need a DQS output.  The memory device will use the AM62Lx OSPI0_LBCLKO as its clock source.  The memory device will be located as close to the far-end of the data bus as possible, and connected such that it doesn’t introduce any stubs on the signals.  The memory device is expected (will need) to operate at reduced data transfer rates because it is located in the middle of the signal traces and will encounter signal distortion caused by reflections from stubs.  The maximum data transfer rate must be determined based on the how long it takes for the data signals to settle for a specific board layout implementation.

Configuring x2 memory devices

The OSPI0 peripheral needs to be configured to communicate with one memory device at a time.  When changing memory devices, the communications channel needs to be gracefully torn-down, the OSPI0 peripheral subsystem is reset, any AM62Lx IOs configuration changes are applied, and the OSPI0 peripheral is reinitialized to operate with the other memory device.  The memory device change is only expected during the AM62Lx boot sequence, where the initial boot image resides in a QSPI or OSPI memory device operating in Tap mode.  After the system boots, the operating system will change to an OSPI memory device operating in one of the faster data transfer modes for run-time storage.

Series resistor on the clock output

There is no specific requirement for series resistors unless the board designer performs a signal quality simulation and finds a series resistor is need to resolve signal distortion.  There is a possibility that series resistors are need on the far-end of the signals if the memory device attached the far-end has a source impedance that is significantly lower than the signal trace impedance.

As a good design practice, it is recommended to provision for a series resistor for the clock output near to the processor clock output pin

Terminating the OSPI0 interface Chip select, Clock, INT# and data signals

Each of the two devices will have their own chip select and clock signals. 

The recommendation is to pull memory device chip select high since the input has an active low function. The recommended location for the pull-up is near the input that would be floating when the signal is not driven (near the memory device).   

The recommendation is to pull memory device clock input low. The recommended location for the pulldown is near the input that would be floating when the signal is not driven (near the memory device).   

The recommendation is to pull memory device data signals D0..D7 (depends on the interface used). There is no preference of location for pull-up placement on the data signals since the signals are bidirectional, and there are times when the signals are not driven by any device.  In this case, all device inputs would be floating without the pull-up resistors.  The biggest difference between the data signals and the chip select and clock signals is the logic state of the data signals are only relevant when they are being driven by one of the devices.  Therefore, we are not worried about noise changing the logic state while no device is actively driving the data signals.  The biggest concern is making sure customers do not create stubs when connecting any of the pull resistors.  One end of each pull resistor should be attached directly to its signal and the other end of the resistor should be routed to the nearest appropriate power rail.  I’m basically saying any signal trace required to connect the pull resistor should be added to the power side rather than the signal side of the resistor.

The recommendation is to place the pullup for the INT# (open drain output) near to the processor input the interrupt input connects.   The resistor needs to be near the floating input to prevent noise changing its logic state.  The INT# pins on the memory device are outputs, not inputs. 

 Connecting x2 OSPI or QSPI memory devices

There is no hardware reason that prevents using two OSPI devices.  The one connected to the far-end of the bus should be the one configured to operates at a faster data transfer rate and needs its DQS output connected to the AM62Lx OSPI0_DQS input.  The other OSPI device will operate in Tap mode at a slower data transfer rate, so its DQS can be left unconnected since Tap mode doesn’t use this signal and the AM62Lx device only have one DQS input.  There may be some software limitations that need to be considered.  We may need to discuss this topic with the software team.

 Two QSPI devices can be connected, but there may be further limitations with data transfer rates since most QSPI devices do not have a DQS output.  Therefore, it may not be possible for the QSPI device connected to the far-end of the bus to operate at the same speed of a OSPI device that has a DQS output which can be connected the AM62Lx DQS input and used to capture receive data.  Again, there may be some software limitations that need to be considered.

Recommended pullup or pulldown values

The recommendation is to follow the pull value in the EVM as a starting point. The board designer is responsible for selecting pull resistor values to meets the requirements of their specific system implementation.

 Need for placing the pull resistor near the pin that is floating

Let me explain why it is better to place the pull resistor near the pin that is floating.  We need an external resistor on the chip select and clock signals to prevent the memory inputs from floating since the IOs associated with the OPSI host are turned off (not driven) by default.  These pulls will hold a valid logic state on the chip select and clock signals until software initializes the OSPI host and associated IOs.  It is very difficult to induce a potential that causes problems when a signal is actively driven because it will have a very low impedance to VDD or VSS.  That may not be the case if noise were to couple to a signal trace while not actively driven.  When not actively driven, noise may induce a voltage potential on the signal and the highest impedance end of the signal trace will see the largest potential.  Placing the pull near the memory device minimizes the voltage potential that can be induced at the memory device end of the signal trace.  This makes it harder for noise to cause a logic state change at the memory device input.  We do not want noise to induce an active low state on the chip select input of the memory device since this could cause it to do something unpredictable.  With this connectivity topology, noise would induce the larger potential on the OSPI host IO.  This can be problematic for the OSPI host IOs if the induced potential exceeds the Absolute Maximum Ratings limits of the IO cell.  If this happens the system designer will need to find a way to eliminate or reduce noise coupling

What is the reason we selected pulldown instead of pullup for OSPI0 or other peripherals?

Because there are cases where the clock is stopped or paused in a low logic state and the pull-down option is consistent with this logic state.

Regards,

Sreenivasa