AM35xx interface to LPDDR

The TRM and DS for the AM35xx is very unclear on LPDDR (mDDR) vs DDR2 interfacing - notes and diagrams on DDR2 but no reference to "do the same for LPDDR" or how to differ. This is also true for the Wiki (http://processors.wiki.ti.com/index.php/AM3517/05_SDRC_Subsystem) where the DDR2 diagram shows PADREF, VREFSSTL, and the STRBEN loops, yet the LPDDR diagram shows none of these, still has the processor labeled as "OMAP3", and has conflicting text stating the STRBEN loops *are* used (despite their absence in the diagram).

Finally, questions ...

- Are the STRBEN to STRBEN-DLY loops used when the SDRC is configured for LPDDR? Match these to the DQS lengths?

- I found a post that the PADREF *is* used (50ohms to ground) for LPDDR.

- What about the VREFSSTL? Bias to 0.5*VDD for DDR2, but do the same for LPDDR?

Thanks ... Jim