Tool/software:
Hi TI Support,
I am trying to enable a watchdog device during all stages of the bootloader. I am able to configure RTI0 for the A53 core (u-boot SPL and u-boot image). Additionally, I would also like to have a watchdog configured for the wakeup domain bootloader (tiboot3.bin) on the R5F core, and this is the part where I am having some trouble.
Useful Reference, I experiencing something similar:
AM62P: Watchdog support in U-Boot (R5) SPL - Processors forum - Processors - TI E2E support forums
Testing:
Based on the am64 evm, in the A53 u-boot defconfig, I added:
CONFIG_WDT_K3_RTI=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_WDT=y
CONFIG_SPL_WDT=y
CONFIG_SPL_WATCHDOG=y
In u-boot device tree I have the rti pins configured the same as the k3-am64* device trees, and I added the following as well:
&main_rti0 {
bootph-pre-ram;
};
&main_rti1 {
status = "disabled";
};
I have been using this configuration option CONFIG_WATCHDOG in my testing. I set it to `=n` so that the watchdog will not get serviced. I am using dfu-util to load the binaries. Using the above configurations, the watchdog works as expected for the A53 SPL and u-boot proper stages. E.g. after loading tiboot3.bin and then tispl.bin, I wait for >60 seconds and it gets reset. Same thing for u-boot.img.
I then decided to add the same defconfig options to the R5 defconfig. As before, I see the message that the watchdog has started (WDT: Started watchdog@e000000 without servicing (60s timeout)). However, the watchdog never fires to trigger a reset after the timeout. Additionally, I can load tispl.bin, but after that, can no longer boot to Linux. The device seems stuck and needs to be power cycled.
Questions:
Do you see anything I might be missing in my configurations or testing? As I mentioned, I have been using DFU, are you aware of this method preventing watchdog reboots?
Perhaps the ROM code automatically sets up a watchdog, and thus enabling a watchdog device on the R5 is NOT something I myself need to enable?
From the AM64x documentation,
"DMSC ROM sets up a 3-minute watchdog timer (MCU_RTI0) timeout. During this time, the MCU boot needs to get completed, otherwise a WDT reset will occur. Once the R5 image is loaded (SBL/SPL), DMSC ROM will restart the watchdog timer for additional 3 minutes upon entering the R5 SBL. The customer-provided MCU image needs to load and install the TI-provided SYSFW image into the DMSC, which will manage the watchdog timer during run time."
