J721S2XSOMXEVM: SERDES0 configuration with 4 PCIe lanes

Mahesh Mayappa

Part Number: J721S2XSOMXEVM

Tool/software:

Dear Team,

We are bringing up Customer specific board that has J721S2

Please provide the sample source code or documents on

1) SERDES0 configuration

2) 4 -PCIe Lane enablement on SERDES0

Thanks & Regards,
Mahesh Mayappa

9 months ago

0 Takuma Fujiwara 9 months ago

TI__Guru 54853 points

Hi Mahesh,

Public documentation of Torrent SERDES from Cadence is part of the TRM. NDA material for the Cadence IP cannot be shared unless you have a NDA with Cadence. However, J721S2 should be using the same Torrent SERDES PHY and PCIe IP as J784S4. Perhaps your colleague might have more information?

The PCIe driver we have for Linux only:

Linux kernel source we have published here: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-6.6.y
And SDK documentation has a diagram that shows relation of each file related to PCIe driver, along with path: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j721s2/10_01_00_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_Root_Complex.html

Regards,

Takuma

0 Mahesh Mayappa 9 months ago in reply to Takuma Fujiwara

Prodigy 80 points

Hi Takuma,

After utilisatioin of PCIe driver configuration I tried to read PCIe controller local management registers PCIE_CORE_LM

PL_CONFIG_0 ==>

LS =0
LTSSM=0

Please let me know what could be the reason for the above Link state is down.
Should I do manual PCIe hw_reset ?

Thanks &Regards,
Mahesh Mayappa

0 Takuma Fujiwara 9 months ago in reply to Mahesh Mayappa

TI__Guru 54853 points

Hi Mahesh,

I see there is a separate thread for this. Let us continue the conversation there.

Regards,

Takuma

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J721S2XSOMXEVM: SERDES0 configuration with 4 PCIe lanes