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the 6455 SRIO buffering structure

hong ma71853
Prodigy 80 points

 hi,

          I am reading the spru967e document about the TI6455 SRIO. I am rather confused about the buffering structure in the SRIO block diagram. what is the difference about 4.5KB shared buffer and the logical layer buffer below the UDI? why make the payload move twice above the physical layer?

          Can anyone help me ?

                                                                                                                                                                              Samantha

  • 0
    TI__Guru* 84110 points

    Samantha,

    Could you please state a reference in the spru967e document to which you make this reference?

    This will help with understanding the type of SRIO transaction that you care about, and the response in the SRIO peripheral may be different depending on that transaction type.

    Regards,
    RandyP