512MB DDR2 memory with AM3359

Miha Gostencnik said:

EMIF supports max 2Gb (256MB) of memory

2Gb or 256MB is the size of the memory device. Using the chip select signal of the memory controller you can connect two of those and get 512MB.

Regards,

Vaibhav

Hello,

I've read EMIF section some more and saw that there is only one CS ("spruh73a.pdf", Section 7.3.1.2, Table7-98 States: Multiple DDR banks -> Only 1 CS/ODT pinned out) out of DDR memory controller.

On BeagleBone board there is a 256MB(128Mx16) device with a 14bit Address bus (A[13:0]) where AM3359 maximum addresses pinout is actually 16bit wide. On the other-hand, DDR3 modules from Micron supports 512MB(256Mx16) parts but this now contradicts with "Memory device capacity of 2Gb" statement from the datasheet (Section 7.3.1.1).

Am I missing something?

Thank you very much for your help and have a nice day,

Miha

Hello,

Yes, there is only 1CS but you can connect two memory devices (2Gb each) on this to get overall 512MB. AM335x EVM has 512MB populated, You can check the DDR connections on the EVM for reference when the design files become available (around mid December).

Regards,

Vaibhav

Hello,

I somehow cant imagine using one CS with two devices, unless the other is negated. Because in Micron's datasheet states that "CS# enables (registered LOW) and disables (registered HIGH) the command decoder.". Therefore, how would memory controller know if both devices are accessed at the same time, and all addresses lines are connected in parallel.

And another question, why is there a 16bit wide bus on EMIF if max. capacity of a supported memory device is 2Gb?

Must say, that this is my first design with more then one memory device and I bet the solution is very simple, yet I don't see it :) . Can you give me any more pointers about this matter?

Best regards,

Miha

Hello,

Check out section 7.3.3.4 of the TRM.

"The DDR2/3/mDDR memory controller views external DDR2/3/mDDR SDRAM as one continuous block of
memory. This statement is true regardless of the number of memory devices located on the chip select
space."

Since a picture speaks a thousand works, there are also a couple of diagrams in the EMIF section of http://www.ti.com/lit/ug/sprugx7/sprugx7.pdf

I will try to get these added in the AM335x TRM also.

Regards,

Vaibhav

Ok, thank you for explanation; just to see if my thinking is correct.

I would bassicly need to connect two devices with narrower 8bit wide data bus (eg.256Mx8 (2Gb)) instead of two 128Mx16 (2Gb) on the same CS and distinguish them with different strobe/mask selection (DQS1:0,DQSn1:0 and DGM1:0), because AM3359 data bus is 16bit wide and there is only one CLK signal.

CS, CLK, CLK#, CKE, ODT, CAS#, RAS#, WE, BA[2:0] and A[14:0] signals are the same for both 8bit parts, where strobe/mask and Data bus are separated:

(eg. part 1: D[7:0] -> AM3359 D[7:0];

part 2: D[7:0] -> AM3359 D[15:8] ).

Another question:

"Table 2-1: L3 Memory map" states that EMIF0 SDRAM can allocate 1GB + additional 1GB reserved space; is it possible to connect two 4Gb (512Mx8) density parts to get a total of 1GB of memory or is 2Gb per device a MAX? With 4Gb devices I mean DDR3, since I believe DDR2 with 4Gb size is a twin die and has common strobe/mask signals and different CS.

As a side note, in "am3359.pdf" document there is a functional block diagram on page 5 and the maximum frequency of memory interface is 303MHz, shouldn't there be written 333MHz? Typo?

Best regards,

Miha

Hello,

Although the EMIF can only support up to 2Gbit devices, I understand that one can use four 512M x 4bit 2Gbit devices. This would allow a full 1GByte of RAM to be attached, which I understand the chip can support. All four devices would be enabled by the same chip select, with two devices sharing DQM[0] and the other two sharing DQM[1], to deliver the upper and lower bytes, as appropriate.

The datasheet (http://www.ti.com/lit/gpn/am3358 and http://www.ti.com/litv/pdf/sprs717 )feature summary says: (By the way, why are there 2 different links to the same sheet? They load as am3358.pdf and sprs717.pdf. This is confusing)

External Memory Interfaces (EMIF)
– mDDR/DDR2/DDR3 Controller:
• mDDR: 200-MHz Clock (400-MHz Data Rate)
• DDR2: 266-MHz Clock (532-MHz Data Rate)
• DDR3: 303-MHz Clock (606-MHz Data Rate)
• 16-Bit Data Bus
• 1 GB of Total Addressable Space
• Supports One x16, Two x8, or Four x4
Memory Device Configurations

Section 5.6.1 only shows the connection of 2 devices in a balanced T. Can anyone confirm that the configuration that I have outlined with four devices will work OK?

I note that the above summary shows DD3 with a 303MHz Clock as the maximum.

Under section 5.6.1.1  Board Designs there is Table 5-28 and Figure 5.4.2. This is supposed to show the timing for the DDR clock period.

I find this table baffling:

First of all it shows "-1G" in the top right of the table. What does this mean?
It shows that the maximum clock period of the DDR clock is 8 ns. I presume this means that the DDR memory must be clocked at a minimum 125MHz to work.

It then shows that the minimum clock period of the DDR clock is 3.67ns. This corresponds to a clock frequency of 272.5MHz. This is nothing like the 303MHz  the datasheet says is the maximum elsewhere. Can someone explain this please?

Thanks,

Roger.

The AM335x data manual will be updated soon to remove support of four x4 memory devices.

The 303MHz clock frequency for DDR3 is correct.  This is the minimum frequency supported by all DDR3 devices and is defined in the DDR3 JEDEC specification.

I will need to discuss your Board Design section questions with someone before answering these questions.  I think this section was copied from another data manual and a few things were not updated to correctly represent AM335x devices.  Hopefully I can answer these questions in a few days.

Regards,

Paul

Hi Paul, thank you for looking into this.

I take it from that, that for some reason support for four x4 devices is not possible. Why this is is not yet clear to me.

Anyway can not 1GB be constructed with two 4Gbit x8 width devices?

The AM335x has 16 DDR address lines pinned out. The datasheet does not say that 4Gb devices are supported, but the datasheet appears to indicate that the chip has the required functionality to do so.

A 4Gbit 512Mx8 Micron device e.g. MT41J512M8THD-15E requires a 64k row address(16 bits), 1k column address(10-bits) and 8 banks(a 3-bit address). The chip has the registers and the pins to support this. Can one not use two of these chips then for 1GByte of RAM?

Regards,

Roger.

Hi Paul,

did you receive any response to your question? I am also considering the AM3359 for  design but I would like to have 1GB of memory as an option.

Regards,

Mike Cruse

Hi Mike,

No I did not yet get a definitive confirmation to my suggestion that one could use two 512Mx8 devices to provide 1GByte of RAM.

If someone could please confirm that this will work, that would be helpful.

The use of four devices appears to be disallowed because of bus loading and/or timing issues.

Regards,

Roger.