• State
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 188 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PROCESSOR-SDK-AM62X: Is there any information about SPI0 that I can refer to?

Daniel Cheng1
Mastermind 7305 points
Part Number: PROCESSOR-SDK-AM62X


Tool/software:

Hi Expert,

The customer will control SPI0 at the Kernel/Driver layer to communicate with the FPGA.

This communication needs to be very real-time. After SPI is written, it has to wait for the received result.

It needs to perform multiple read and write operations every 125us.

Where will the setting of SPI0 be? As for how to call and use it, are there any similar related examples for reference?

Thanks

Daniel

  • 0
    TI__Guru 70082 points

    Hi Daniel,

    How much data are you trying to transfer? Can you describe this in a bit more detail (a typical example, perhaps)
    Doing SPI transfers in Linux gets tricky to do in a real-time fashion if your latency requirements are tight.

    Regards, Andreas

  • 0 in reply to Andreas Dannenberg
    Mastermind 7305 points

    Hi Andreas

    The communication protocol is very complex. The customer presents the control sequence in a diagram, hoping it will be easier to understand.

    Customers know that it is difficult to implement in Linux. In their existing products, they are also implemented in Linux Driver.

    The customer directly controls the SPI related Register in the CPU to achieve the purpose. The following part of the program code

    This is implemented in Cavium CN7020 1GHz:

    Can you see the control sequence in a diagram file I sent you via message?

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    TI__Guru 70082 points

    Hi Daniel,

    Daniel Cheng1 said:
    Can you see the control sequence in a diagram file I sent you via message?

    I got the file, it is detailed and easy to understand, thank you.

    I need to spend some time to digest everything but the easiest might be to create a proof of concept really to try out how well it works. From the screenshot it looks like you may already have Linux code/driver?

    On a high level, there are two potential challenges:

    Effective SPI Throughput

    You say SPI speed between CPU <-> FPGA is limited to 12MHz, but it seems like it should be possible to make it faster if needed, since the customer controls both ends of the communication, no?

    The document also says DMA mode cannot be used. If you are using AM62'x SPI module in our current SDK without DMA mode, there will be "inter-byte gaps" during the transmission, reducing your effective throughput. Usually customers can increase the SPI speed to work around this, or use the DMA. Note that the length of those gaps is depending on your configured SPI clock frequency (higher frequency -> shorter gaps)

    Here's some info and example on how DMA helps reducing those "inter-byte gaps": https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1356551/faq-am6x-optimizing-spi-transfer-inter-byte-gaps-using-the-dma-in-linux

    Real-Time Behavior

    Seems like there are a lot of hard realtime requirements in your recurring transmission every 125us including multi-byte send/processing/receive activities. Generally speaking tight hard headlines are difficult to meet with regular Linux where interrupt and task-switch latencies can be in the 100's of us. Two potential options...

    1. Using Linux RT (which we also offer for AM62) can bring a dramatic improvement on this front by minimizing system-induced latencies into 10's of us, see here https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/10_01_10_04/exports/docs/devices/AM62X/linux/RT_Linux_Performance_Guide.html   This alone may or may not be enough what you need.

    2. Another option is to use an RTOS-based approach to drive that SPI communication using a dedicated communication task. This could be done by using a hypervisor approach (Jailhouse, we offer this as well for AM62) to partition off on A53 core to do your SPI communication work. Or, potentially by using one of the dedicated real-time cores ("PRU") on the device or the M4 MCU core.

    Regards, Andreas