AM6442: How to enter PCIe compliance test mode on AM64x

Hi Rich Chen,

Assuming your query is hardware specific. Forwarding your thread to PCIE-HW expert.

Are you working on Linux / RTOS?

Regards

Ashwani

Ashiwani, 

Linux is current working on.  

In customer size, as long as they can complete the compliance test in lab to make sure their hardware can pass certification.

Linux or Windows environment will be expected, JTAG via CCS is not preferred due to JTAG usually not be reserved. 

BR, Rich 

the endpoint device will get placed into compliance mode by setting 'EC' bit [4] of I_LINK_CTRL_STATUS_2 register and initiating a hot reset.   (see TRM Table 12-2082)

Regards,

James

James, 

This register indicates endpoint enter compliance mode. 

Does Root Controller mode also can be tested by this?

BR, Rich 

Hi Rich,

It's the same for Root Complex, there will need to be termination to compliance load. So if you have lane terminated into 50ohm scope and with EC bit set, then transmit of compliance pattern should occur.    

James, 

Have we ever tried this setting on AM64x GP EVM with PCIe slot in RC mode? 

Customer reported adding lane terminated to 50 ohm still not getting compliance test pattern generated from AM64x. 

My understanding to set this bit is forcing EP device to enter compliance mode but there is no EP device on PCIe bus (slot). 

Customer would like to test RC TX signal SI and it seems we need different way to enable it. 

BR, Rich 

we have only performed PCIE compliance using combination equipment of Keysight M8041A (high performance BERT) + Keysight DSA Infinium scope + Keysight PCIE compliance test package and also with using bare-metal code

James, 

I discussed this with our PCIe re-timer FAE and learn the way you test is for RX which Keysight M8041A (high performance BERT) send out signals to our SOC and PCIe controller will be set to loopback mode so signals will be sent out from our SOC to test equipment which is Keysight DSA infinium scope + Keysight PCIe compliance test package. 

The signals are looping back and be sent out by our SOC so it will be TX signals. 

The bare-metal code is used to set our SOC PCIe controller into RC and loopback mode. 

This test could be called "RX" test and it requires the BERT device which is very expensive and most of our customers will not have the equipment. 

Besides, customer thinks test TX only will be enough because from customer side, they need a way to verify the signal output from RC Signal Integrity so TX mode test will be easier to achieve and in this test mode I believe only the Keysight DSA infinium scope + Keysight PCIe compliance test package is required. 

This is also the est way most of our customer will do for PCIe compliance test.  

Next, the problem why we cannot enter compliance mode via set EC bit[4] of I_LINK_CTRL_STATUS_2 register to get placed into compliance mode?

He mentioned PCIe RC and EP will have chance to enter compliance test mode only first time boot and doing negotiation. 

After negotiation, RC or EP will enter L0 and never have chance to enter compliance test mode unless reboot. 

I am thinking to set this EC bit in u-boot first then boot Linux after changing this bit. 

No sure whether this will work because thneeds to be test in customer side with test equipment.  

Will we be able to test TX mode in lab with Linux commend? I would like make sure whether the assumption is correct and compliance TX test mode can be conducted under Linux.  

BR, Rich

Hi Rich,

In August timeframe we again will be perfoming PCIE compliance test and I agree it will be good if we can get Linux code that would enable this which can then be used by customer as well.