AM625: Running MCASP as master with external AUDIO_EXT_REFCLK of 24.576MHz

António Oliveira

Part Number: AM625
Other Parts Discussed in Thread: TAS5802, PCM5102A,

Tool/software:

Hi all,

I've been trying to set up mcasp2 on the AM6254 as master, using an external 24.576MHz clock that feeds AUDIO_EXT_REFCLK0 input of the SoC on ball AE22.

The codec on our custom board is a TAS5802, and MCASP2 drives ACLKX, AFSX and AXR0. For the scope of this question I used a PCM5102a and would like to observe the signals on a scope with either aplay or speaker-test, leaving the TAS5802 as a topic for a separate question.

aplay -l shows:

**** List of PLAYBACK Hardware Devices ****
card 0: InternalSpeaker [Internal-Speaker], device 0: davinci-mcasp.0-pcm5102a-hifi pcm5102a-hifi-0 [davinci-mcasp.0-pcm5102a-hifi pcm5102a-hifi-0]
Subdevices: 1/1
Subdevice #0: subdevice #0

And I can execute play -D plughw:0,0 -c 2 -r 48000 -f S16_LE /dev/zero apparently without errors.

Attaching a scope probe into the MCASP2 signals I get:

ACLKX: 6.25MHz

AFSX: 192.315kHz

The framing seems correct: 32 bit clocks per frame, or 2 tdm slots per frame, but the base clock is clearly derived from the system clock (25M/4) while I'd like to see it derived from the 24.576M REFCLK0

At this point this is the relevant portion of my device tree:

/ {
	fixed_audio_refclk: clk-0 {
		status = "okay";

		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24576000>;
	};
	
    pcm5102a: pcm5102a {
		compatible = "ti,pcm5102a";
		#sound-dai-cells = <0>;
	};

	board_speakers: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "Internal-Speaker";

		simple-audio-card,bitclock-master = <&mcasp2>;
		simple-audio-card,frame-master = <&mcasp2>;
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp2>;
			system-clock-frequency = <24576000>;
			system-clock-direction-out;
		};

		simple-audio-card,codec {
			sound-dai = <&pcm5102a>;
		};
    };


};

&main_pmx0 {
	pinctrl-names = "default";
	pinctrl-0 = <&board_pins_refclk>;

	board_pins_mcasp2: board-pins-mcasp2 {
		pinctrl-single,pins = <
			AM62X_IOPAD(0xf41d0, PIN_OUTPUT, 8) /* [Speaker_Audio_FSYNC] (A15) UART0_CTSn.MCASP2_AFSX */
			AM62X_IOPAD(0xf41d4, PIN_OUTPUT, 8) /* [Speaker_Audio_CLK] (B15) UART0_RTSn.MCASP2_ACLKX */
			AM62X_IOPAD(0xf41d8, PIN_OUTPUT, 8) /* [Speaker_Audio_OUT] (C15) MCAN0_TX.MCASP2_AXR0 */
		>;
	};

	board_pins_refclk: board-pins-refclk {
		pinctrl-single,pins = <
			AM62X_IOPAD(0xf4190, PIN_INPUT, 2) /* [Audio_EXT_Refclk0] (AE22) RGMII2_RD3.AUDIO_EXT_REFCLK0 */
			AM62X_IOPAD(0xf41f0, PIN_INPUT, 0) /* [Ext_Refclk1] (A18) EXT_REFCLK1.EXT_REFCLK1 */
			AM62X_IOPAD(0xf413c, PIN_OUTPUT, 7) /* [Audio_Refclk_Enable] (AE18) RGMII1_TD2.GPIO0_77 */
		>;
	};
	
};

&main_gpio0 {
	audio_refclk_enable {
		gpio-hog;
		gpios = <77 GPIO_ACTIVE_HIGH>;
		output-high;
	};
};

&mcasp2 {
	status = "okay";
	#sound-dai-cells = <0>;

	/* CLOCKS:
	 * BOARD_AUDIO_EXT_REFCLK0 <192 12> --> AHCLKR IN <192 9>
	 * BOARD_AUDIO_EXT_REFCLK0 <192 18> --> AHCLKX IN <192 15>
	 * REFCLK runs at 24,576 MHz
	 */
	assigned-clocks        = <&k3_clks 192 9>, <&k3_clks 192 15>;
	assigned-clock-parents = <&k3_clks 192 12>, <&k3_clks 192 18>;
	assigned-clock-rates   = <24576000>, <24576000>;

	pinctrl-names = "default";
	pinctrl-0 = <&board_pins_mcasp2>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;

	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
	       1 0 0 0
	       0 0 0 0
	       0 0 0 0
	       0 0 0 0
	>;
	tx-num-evt = <0>;
	rx-num-evt = <0>;
};

k3conf output for the MCASP2 clocks

data-mode="text">k3conf dump clocks 192 ------------------------------------------------------------| | ------------------------------------------------------------| (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024) | | ABI: 4.0 (firmware version 0x000a '10.1.8--v10.01.08 (Fiery Fox))') | ------------------------------------------------------------| -----------------------------------------------------------------------------------------------------------| | Clock ID | Clock Name | Status | Clock Frequency | -----------------------------------------------------------------------------------------------------------| 0 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 100000000 | 1 | DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | CLK_STATE_READY | 100000000 | 2 | DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 96000000 | 3 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | 4 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | 5 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | 6 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | 7 | DEV_MCASP2_MCASP_AFSR_POUT | CLK_STATE_READY | 0 | 8 | DEV_MCASP2_MCASP_AFSX_POUT | CLK_STATE_READY | 0 | 9 | DEV_MCASP2_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | 10 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 11 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 | 12 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | 13 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 14 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | 15 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | 16 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 17 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 | 18 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | 19 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 20 | DEV_MCASP2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | 21 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | -----------------------------------------------------------------------------------------------------------|

And /sys/kernel/debug/clk/clk_summary (mcasp2 and boardclocks only)

 cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty  hardware                            connection
   clock                          count    count    count        rate   accuracy phase  cycle    enable   consumer                         id
---------------------------------------------------------------------------------------------------------------------------------------------
 clk:192:19                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:18                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
    clk:192:15                       0       0        0        0           0          0     50000      Y      deviceless                      no_connection_id         
 clk:192:17                          0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:16                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:13                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:12                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
    clk:192:9                        0       0        0        0           0          0     50000      Y      deviceless                      no_connection_id         
 clk:192:11                          0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:10                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:2                           0       0        0        96000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:192:1                           0       0        0        100000000   0          0     50000      Y   deviceless                      no_connection_id         
    clk:192:0                        0       0        0        100000000   0          0     50000      Y      deviceless                      no_connection_id         
 clk:191:2                           0       0        0        96000000    0          0     50000      Y   deviceless                      no_connection_id         
 
 and:
 clk:157:166                         0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:165                         0       0        0        12500000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:164                         0       0        0        32768       0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:163                         0       0        0        50000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:162                         0       0        0        192000000   0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:161                         0       0        0        200000000   0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:160                         0       0        0        32768       0          0     50000      Y   deviceless                      no_connection_id         
    clk:157:158                      0       0        0        32768       0          0     50000      Y      deviceless                      no_connection_id         
 clk:157:159                         0       0        0        25000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:18                          0       0        0        100000000   0          0     50000      Y   deviceless                      no_connection_id         
    clk:157:10                       0       0        0        100000000   0          0     50000      Y      deviceless                      no_connection_id         
       audio_refclk:clk:157:10       0       0        0        100000000   0          0     50000      N         deviceless                      no_connection_id         
 clk:157:17                          0       0        0        96000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:16                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:15                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:14                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:13                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:12                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:11                          0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:8                           0       0        0        100000000   0          0     50000      Y   deviceless                      no_connection_id         
    clk:157:0                        0       0        0        100000000   0          0     50000      Y      deviceless                      no_connection_id         
       audio_refclk:clk:157:0        0       0        0        100000000   0          0     50000      N         deviceless                      no_connection_id         
 clk:157:7                           0       0        0        96000000    0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:6                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:5                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:4                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:3                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:2                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:157:1                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id

* How do I let the system know, through the devicetree that fixed_audio_refclk is the input clock to MCASP2?
* Is there anything we should do with the ti,am62-audio-refclk nodes?

If I take the configuration correctly I should have a 48kHz AFSX and 1.536M ACLKX signals. Please advice on which adjustments I need to do on this setup.

Regards,

António

1 month ago

0 Suren Porwar 1 month ago

TI__Mastermind 24115 points

Hi Antonio,

If I understand correctly, you are wanting to use MCASP as producer of BCLK and FSYNC to operate the codec.

Also you are providing the AUDIO_EXT_REFCLK0 externally correct to drive the above clocks from MCASP? Or do you want to configure AUDIO_EXT_REFCLK as output?

Example for configuring the AUDIO_EXT_REFCLK with MCASP0 as output in the device tree would require you to add the below lines:

The pinmux for AUDIO_EXT_REFCLK0 is configurred as below.

AM62X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (E18) MCASP0_AXR0.AUDIO_EXT_REFCLK0 */

The DTS for AUDIO_EXT_REFCLK0 is configurred as below.

assigned-clocks = <&k3_clks 157 0>, <&k3_clks 157 7>;
assigned-clock-parents = <&k3_clks 157 7>;
assigned-clock-rates = <12288000>, <0>;

Hope this helps.

Best Regards

0 António Oliveira 1 month ago in reply to Suren Porwar

Prodigy 155 points

If I understand correctly, you are wanting to use MCASP as producer of BCLK and FSYNC to operate the codec.

That is correct.

Also you are providing the AUDIO_EXT_REFCLK0 externally correct to drive the above clocks from MCASP? Or do you want to configure AUDIO_EXT_REFCLK as output?

I am providing AUDIO_EXT_REFCLK0 from an external oscillator into ball AE22 of the AM6254ALW with a frequency of 24.576MHz. To be clear: **AUDIO_EXT_REFCLK0 is an input**

The DTS for AUDIO_EXT_REFCLK0 is configurred as below.

assigned-clocks = <&k3_clks 157 0>, <&k3_clks 157 7>;
assigned-clock-parents = <&k3_clks 157 7>;
assigned-clock-rates = <12288000>, <0>;

I haven't tried this yet, but from the TISCI page, this seems to configure the REFCLK output of the AM625 as being driven by the "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK" signal of the AM625, with a frequency of 12,288MHz.

Am I interpreting the devicetree snippet correctly?

What I want to do goes in the inverse direction: feed the external 24.576MHz reference clock to the MCASP so that it is able to generate BCLK and LRCLK and drive these signals to the codec.

Kind regards,

António Oliveira.

0 Suren Porwar 1 month ago in reply to António Oliveira

TI__Mastermind 24115 points

Hi Antonio,

assigned-clocks=<&k3_clks 192 9> /*MCASP2_AHCLKR_PIN */

assigned-clock-parents =<&k3_clks 192 12>; /* AUDIO_EXT_REFCLK0_IN */

assignd-clock-rates=<24576000>;

Hope this helps.

Best Regards,

Suren

0 António Oliveira 1 month ago in reply to Suren Porwar

Prodigy 155 points

Thanks, Suren.

This seems to be the same that is in the devicetree snipped I shared. Am I missing something?

My interpretation of the above is that AHCLKR selects AUDIO_EXT_REFCLK0_IN as its input, but then AHCLKX is not configured, leading to potentially misconfigured transmit clock.

In my application we are actually only transmitting audio from the MCASP so it seems that AHCLKX would be the most important clock to be configured.

Please confirm if any of this makes sense and what I may be missing here.

I'll report back with my test results soon.

+1 Suren Porwar 1 month ago in reply to António Oliveira

TI__Mastermind 24115 points

You could change the AHCLKR to AHCLKX with assigned-clocks = <&k3_clks 192 27> and assigned-clock-parents = <&k3_clks 192 30>

Let me know how it goes.

Best Regards,

Suren

+1 António Oliveira 1 month ago in reply to Suren Porwar

Prodigy 155 points

Hi Suren, again, thanks for your hints.

Here's what I tried:

assigned-clocks=<&k3_clks 192 9> /*MCASP2_AHCLKR_PIN */

assigned-clock-parents =<&k3_clks 192 12>; /* AUDIO_EXT_REFCLK0_IN */

assignd-clock-rates=<24576000>;

This didn't change the measured frequencies at all, which wasn't entirely surprising.

I ran out of time at the office, but still managed to try modifying the simple-audio-card-cpu as follows:

simple-audio-card,cpu {
	sound-dai = <&mcasp2>;  
};

After some topics seeming to suggest that system-clock-direction-out causes the MCASP clock to be taken from the internal SoC clock instead of the reference clock. After this test the measured frequencies did change but were outside the expected range (LRCLK=48kHz).

Due to the shortage of time I was unable to note down my measurements or make additional attempts.

Finally, regarding the latest suggestion:

assigned-clocks = <&k3_clks 192 27> and assigned-clock-parents = <&k3_clks 192 30>

I've been trying to figure out the clock tree from the below page:

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html

however I am unable to find references to the above clock identifiers. Is there another resource I should be looking at? Tomorrow morning I'll give a shot at these settings, but knowing where to find the listing/documentation of these clock routing options and identifiers would probably help greatly me and others understanding how to properly set up the clocks for this use case.

All the best,

António

0 Suren Porwar 1 month ago in reply to António Oliveira

TI__Mastermind 24115 points

Hi Antonio,

Were you be able to validate it on your end?

Best Regards,

Suren

0 António Oliveira 28 days ago in reply to Suren Porwar

Prodigy 155 points

Hi Suren,

This worked! Thank you!

I had to set the clocks in the devicetree, as follows:

assigned-clocks        = <&k3_clks 192 9>, <&k3_clks 192 15>, <&k3_clks 192 27>;
assigned-clock-parents = <&k3_clks 192 12>, <&k3_clks 192 18>, <&k3_clks 192 30>;
assigned-clock-rates   = <24576000>, <24576000>, <0>;

On boot I get this error message on the console:

[ 0.230788] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=192, clk=27, ret=-19
[ 0.230964] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=192, clk=30, ret=-19

But running aplay does show a 48kHz LRCLK and a 1.536Mhz BCLK.

I can't find the description of the clock specifiers <&k3_clks 192 27> and <&k3_clks 192 30>. Would you kindly link me to the page you took the screenshot from?

Best regards,

António

0 Suren Porwar 25 days ago in reply to António Oliveira

TI__Mastermind 24115 points

I am glad it worked. I am going to close this thread. Feel free to reach out for any further assistance.

I took the screenshot from the below mentioned page.

software-dl.ti.com/.../clocks.html

Best Regards,

Suren

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AM625: Running MCASP as master with external AUDIO_EXT_REFCLK of 24.576MHz