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[FAQ] AM625 / AM623 / AM620-Q1 / AM62Ax / AM62D-Q1 / AM62Px / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design – Queries related to Discrete power Architecture

Kallikuppa Sreenivasa
Guru**** 174974 points
Part Number: AM625
Other Parts Discussed in Thread: AM62P, AM62L

Tool/software:

HI TI experts,

We are considering implementing power architecture using discrete DC/DC and LDO.

Do you have some recommendations or recommendation for the below:

1. Power sequencing 

2. Current consumption

3. Supply Slew rate 

4. Process cold reset input control - delay after supply ramp, slew rate and IO level 

5. Power architecture when VDD_CORE is 0.75V and 0.85V 

6. Power architecture when partial IO mode is implemented 

  • +1
    TI__Guru**** 174974 points

    HI Board designers, 

    1. Power sequencing 

    The recommendation is to follow the Power Supply Sequencing section of the processor-specific data sheet. 

    2. Current consumption

    AM625

    AM62x Maximum Current Ratings

    https://www.ti.com/lit/pdf/sprada6

    AM62A

    AM62Ax Maximum Current Ratings

    https://www.ti.com/lit/pdf/sprada7

    AM62D

    AM62P

    AM62L

    AM62L Maximum Current Ratings

    https://www.ti.com/lit/pdf/spradr4

    3. Supply Slew rate 

    Follow the Power Supply Slew Rate Requirement section of the processor-specific data sheet. 

    4. Process cold reset input - delay after supply ramp, slew rate and IO level 

    A delay specified in the data sheet after all the supplies ramp for clock to start-up and settle is required to be provided before the Power Good output from the discrete DC/DC connects to the MCU_PORz (PORz for AM62L) input.

    This is a cold reset input and has internal hysteresis. A slow ramp input could glitch the internal reset. Minimize the slew rate or use a fast rise time discrete push pull output buffer with hysteres