the following code is for the "EDMA transfer complete interrupt " global region
it doesn't work correctly. the EDMA interrupt could not work.
please help me what is the fault?
#define EDMA3_CC0_BASE 0x02700000
#define EDMA3_CC1_BASE 0x02720000
#define EDMA3_CC2_BASE 0x02740000
#define EDMA3_0_TC0_BASE 0x02760000
#define EDMA3_0_TC1_BASE 0x02768000
#define EDMA3_1_TC0_BASE 0x02770000
#define EDMA3_1_TC1_BASE 0x02778000
#define EDMA3_1_TC2_BASE 0x02780000
#define EDMA3_1_TC3_BASE 0x02788000
#define EDMA3_2_TC0_BASE 0x02790000
#define EDMA3_2_TC1_BASE 0x02798000
#define EDMA3_2_TC2_BASE 0x027a0000
#define EDMA3_2_TC3_BASE 0x027a8000
///////////////////////////EDMA3 chanel comtrol//////////////////////////////////////////////////
#define CCPID 0x0000 //Peripheral Identification Register
#define CCCFG 0x0004 //EDMA3CC Configuration Register
#define DCHMAP 0x0100 //DCHMAP0-63 DMA Channel 0-63 Mapping Registers
#define QCHMAP0 0x0200 //QDMA Channel 0 Mapping Register
#define QCHMAP1 0x0204 //QDMA Channel 1 Mapping Register
#define QCHMAP2 0x0208 //QDMA Channel 2 Mapping Register
#define QCHMAP3 0x020C //QDMA Channel 3 Mapping Register
#define QCHMAP4 0x0210 //QDMA Channel 4 Mapping Register
#define QCHMAP5 0x0214 //QDMA Channel 5 Mapping Register
#define QCHMAP6 0x0218 //QDMA Channel 6 Mapping Register
#define QCHMAP7 0x021C //QDMA Channel 7 Mapping Register
#define DMAQNUM0 0x0240 //DMA Queue Number Register 0
#define DMAQNUM1 0x0244 //DMA Queue Number Register 1
#define DMAQNUM2 0x0248 //DMA Queue Number Register 2
#define DMAQNUM3 0x024C //DMA Queue Number Register 3
#define DMAQNUM4 0x0250 //DMA Queue Number Register 4
#define DMAQNUM5 0x0254 //DMA Queue Number Register 5
#define DMAQNUM6 0x0258 //DMA Queue Number Register 6
#define DMAQNUM7 0x025C //DMA Queue Number Register 7
#define QDMAQNUM 0x0260 //QDMA Queue Number Register
#define QUEPRI 0x0284 //Queue Priority Register
#define EMR 0x0300 //Eent Missed Register
#define EMRH 0x0304 //Event Missed Register High
#define EMCR 0x0308 //Event Missed Clear Register
#define EMCRH 0x030C //Event Missed Clear Register High
#define QEMR 0x0310 //QDMA Event Missed Register
#define QEMCR 0x0314 //QDMA Event Missed Clear Register
#define CCERR 0x0318 //EDMA3CC Error Register
#define CCERRCLR 0x031C //EDMA3CC Error Clear Register
#define EEVAL 0x0320 //Error Evaluate Register
#define DRAE0 0x0340 //DMA Region Access Enable Register for Region 0
#define DRAEH0 0x0344 //DMA Region Access Enable Register High for Region 0
#define DRAE1 0x0348 //DMA Region Access Enable Register for Region 1
#define DRAEH1 0x034C //DMA Region Access Enable Register High for Region 1
#define DRAE2 0x0350 //DMA Region Access Enable Register for Region 2
#define DRAEH2 0x0354 //DMA Region Access Enable Register High for Region 2
#define DRAE3 0x0358 //DMA Region Access Enable Register for Region 3
#define DRAEH3 0x035C //DMA Region Access Enable Register High for Region 3
#define DRAE4 0x0360 //DMA Region Access Enable Register for Region 4
#define DRAEH4 0x0364 //DMA Region Access Enable Register High for Region 4
#define DRAE5 0x0368 //DMA Region Access Enable Register for Region 5
#define DRAEH5 0x036C //DMA Region Access Enable Register High for Region 5
#define DRAE6 0x0370 //DMA Region Access Enable Register for Region 6
#define DRAEH6 0x0374 //DMA Region Access Enable Register High for Region 6
#define DRAE7 0x0378 //DMA Region Access Enable Register for Region 7
#define DRAEH7 0x037C //DMA Region Access Enable Register High for Region 7
#define QRAE0 0x0380 //QDMA Region Access Enable Registers for Region 0-7
#define Q0E0 0x0400 //Event Queue Entry Registers Q0E0-Q3E15
#define QSTAT0 0x0600 //Queue Status Registers 0-3
#define QWMTHRA 0x0620 //Queue Watermark Threshold A Register
#define CCSTAT 0x0640 //EDMA3CC Status Register
#define MPFAR 0x0800 //Memory Protection Fault Address Register
#define MPFSR 0x0804 //Memory Protection Fault Status Register
#define MPFCR 0x0808 //Memory Protection Fault Command Register
#define MPPAG 0x080C //Memory Protection Page Attribute Global Register
#define MPPA0 0x0810 //MPPA0-7 Memory Protection Page Attribute Registers 0-7
//Global Region Registers
#define GLOBAL_RRB 0x1000
#define ER 0x1000 //Event Register
#define ERH 0x1004 //Event Register High
#define EDMAECR 0x1008 //Event Clear Register
#define ECRH 0x100C //Event Clear Register High
#define ESR 0x1010 //Event Set Register
#define ESRH 0x1014 //Event Set Register High
#define CER 0x1018 //Chained Event Register
#define CERH 0x101C //Chained Event Register High
#define EER 0x1020 //Event Enable Register
#define EERH 0x1024 //Event Enable Register High
#define EECR 0x1028 //Event Enable Clear Register
#define EECRH 0x102C //Event Enable Clear Register High
#define EESR 0x1030 //Event Enable Set Register
#define EESRH 0x1034 //Event Enable Set Register High
#define SER 0x1038 //Secondary Event Register
#define SERH 0x103C //Secondary Event Register High
#define SECR 0x1040 //Secondary Event Clear Register
#define SECRH 0x1044 //Secondary Event Clear Register High
#define EDMAIER 0x1050 //Interrupt Enable Register
#define IERH 0x1054 //Interrupt Enable Register High
#define IECR 0x1058 //Interrupt Enable Clear Register
#define IECRH 0x105C //Interrupt Enable Clear Register High
#define IESR 0x1060 //Interrupt Enable Set Register
#define IESRH 0x1064 //Interrupt Enable Set Register High
#define IPR 0x1068 //Interrupt Pending Register
#define IPRH 0x106C //Interrupt Pending Register High
#define EDMAICR 0x1070 //Interrupt Clear Register
#define ICRH 0x1074 //Interrupt Clear Register High
#define IEVAL 0x1078 //Interrupt Evaluate Register
#define QER 0x1080 //QDMA Event Register
#define QEER 0x1084 //QDMA Event Enable Register
#define QEECR 0x1088 //QDMA Event Enable Clear Register
#define QEESR 0x108C //QDMA Event Enable Set Register
#define QSER 0x1090 //QDMA Secondary Event Register
#define QSECR 0x1094 //QDMA Secondary Event Clear Register
//
#define PaRAM 0x4000 //PaRAM set 0 to 401Fh
#define PaRAMOPT 0x0000 //
#define PaRAMSRC 0x0001 //
#define PaRAMABCNT 0x0002 //BCNT ACNT
#define PaRAMDST 0x0003 //
#define PaRAMIDX1 0x0004 //DSTBIDX SRCBIDX
#define PaRAMRLD 0x0005 //BCNTRLD LINK
#define PaRAMIDX 0x0006 //DSTCIDX SRCCIDX
#define PaRAMCCNT 0x0007 //Rsvd CCNT
#define CHIP_LEVEL_REG 0x02620000
#define KICK0 (CHIP_LEVEL_REG + 0x0038)
#define KICK1 (CHIP_LEVEL_REG + 0x003C)
#define MAINPLLCTL0 (CHIP_LEVEL_REG + 0x0328)
#define MAINPLLCTL1 (CHIP_LEVEL_REG + 0x032c)
#define DDR3PLLCTL0 (CHIP_LEVEL_REG + 0x0330)
#define DDR3PLLCTL1 (CHIP_LEVEL_REG + 0x0334)
#define PLL1_BASE 0x02310000
#define PLL1_RSTCTL (PLL1_BASE + 0x0e8) // PLL1 Reset Control
#define PLL1_RSTCFG (PLL1_BASE + 0x0ec) // PLL1 Reset Config
#define PLL1_PLLCTL (PLL1_BASE + 0x100) // PLL1 Control
#define PLL1_SECCTL (PLL1_BASE + 0x108)
#define PLL1_PLLM (PLL1_BASE + 0x110) // PLL1 Multiplier
#define PLL1_DIV1 (PLL1_BASE + 0x118) // DIV1 divider
#define PLL1_DIV2 (PLL1_BASE + 0x11C) // DIV2 divider
#define PLL1_DIV3 (PLL1_BASE + 0x120) // DIV3 divider
#define PLL1_CMD (PLL1_BASE + 0x138) // CMD control
#define PLL1_STAT (PLL1_BASE + 0x13C) // STAT control
#define PLL1_ALNCTL (PLL1_BASE + 0x140) // ALNCTL control
#define PLL1_DCHANGE (PLL1_BASE + 0x144) // DCHANGE status
#define PLL1_CKEN (PLL1_BASE + 0x148) // CKEN control
#define PLL1_CKSTAT (PLL1_BASE + 0x14C) // CKSTAT status
#define PLL1_SYSTAT (PLL1_BASE + 0x150) // SYSTAT status
#define PLL1_DIV4 (PLL1_BASE + 0x160) // DIV4 divider
#define PLL1_DIV5 (PLL1_BASE + 0x164) // DIV5 divider
#define PLL1_DIV6 (PLL1_BASE + 0x168) // DIV6 divider
#define PLL1_DIV7 (PLL1_BASE + 0x16C) // DIV7 divider
#define PLL1_DIV8 (PLL1_BASE + 0x170) // DIV8 divider
#define PLL1_DIV9 (PLL1_BASE + 0x174) // DIV9 divider
#define PLL1_DIV10 (PLL1_BASE + 0x178) // DIV10 divider
#define PLL1_DIV11 (PLL1_BASE + 0x17C) // DIV11 divider
#define PLL1_DIV12 (PLL1_BASE + 0x180) // DIV12 divider
#define PLL1_DIV13 (PLL1_BASE + 0x184) // DIV13 divider
#define PLL1_DIV14 (PLL1_BASE + 0x188) // DIV14 divider
#define PLL1_DIV15 (PLL1_BASE + 0x18C) // DIV15 divider
#define PLL1_DIV16 (PLL1_BASE + 0x190) // DIV16 divider
#define INTC0_BASE 0x02600000
//Revision 0x000 Register
//CONTROL_REG 0x4 Control Register
//HOST_CONTROL_REG 0xc Host Control Register
#define HINT_GBL_EN 0x0010 //host interrupt Global Enable Register
#define SINT_ST_IDX_SET 0x0020 //System Interrupt Status Indexed Set Register
#define SINT_ST_IDX_CLR 0x0024 //System Interrupt Status Indexed Clear Register
#define SINT_EN_IDX_SET 0x0028 //System Interrupt Enable Indexed Set Register
#define SINT_EN_IDX_CLR 0x002C //System Interrupt Enable Indexed Clear Register
#define HINT_EN_IDX_SET 0x0034 //Host Interrupt Enable Indexed Set Register
#define HINT_EN_IDX_CLR 0x0038 //Host Interrupt Enable Indexed Clear Register
#define SINT_ST_RAW_SET 0x0200 //System Interrupt Status Raw/Set Registers 160/32 = 5
#define SINT_ST_END_CLR 0x0280 //System Interrupt Status Enabled/Clear Registers 160/32 = 5
#define SINT_ST_EN_SET 0x0300 //System Interrupt Status Enable Set Registers 160/32 = 5
#define SINT_ST_EN_CLR 0x0380 //System Interrupt Status Enable Clear Registers 160/32 = 5
#define SINT_CHL_MAP 0x0400 //Channel Map Registers 160/4 = 40
#define HINT_CHL_MAP 0x0800 //Host Map Registers 76/4 = 19
#define HINT_IDL_EN 0x1500 //Host Interrupt Enable Registers 76/32 = 3
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/src/intc/csl_intcAux.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/csl_cpIntcAux.h>
#define NN 4096
int srcBuff1[4096*2];
void Init_PLL(unsigned int PLLM_val, unsigned int PLLDIV2_val, unsigned int PLLDIV5_val, unsigned int PLLDIV8_val)
{
int i,j;
unsigned int ctl,secctl,pllstatus;
/*Unlock Boot Config*/
*(unsigned int *)KICK0 = 0x83E70B13;
*(unsigned int *)KICK1 = 0x95A4F1E0;
ctl = *(unsigned int *)PLL1_PLLCTL;
ctl &= ~(0x00000031);
*(unsigned int *)PLL1_PLLCTL = ctl;
secctl = *(unsigned int *)PLL1_SECCTL;
secctl |= 1 << 23;
*(unsigned int *)PLL1_SECCTL = secctl;
/*In PLLCTL, write PLLENSRC = 0 (enable PLLEN bit)*/
ctl = ctl | 2;
*(unsigned int *)PLL1_PLLCTL = ctl;
/*In PLLCTL, write PLLEN = 0 (bypass mode)*/
i = 50000;
while (i--) {
asm(" NOP");
}
ctl = ctl & ~2;
*(unsigned int *)PLL1_PLLCTL = ctl;
i = 50000;
while (i--) {
asm(" NOP");
}
/*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/
i = 100;
while (i--) { asm(" NOP"); }
/*In PLLCTL, write PLLRST = 1 (PLL is reset) */
ctl = ctl | (1 << 3);
*(unsigned int *)PLL1_PLLCTL = ctl;
/* Enable the pll divider */
secctl = *(unsigned int *)PLL1_SECCTL;
secctl |= (1 << 16);
secctl |= (1 << 19);
*(unsigned int *)PLL1_SECCTL = secctl;
/*If necessary program PLLM*/
*(unsigned int *)MAINPLLCTL0 = 1 & 0x3f; /* PLLD[5:0] */
*(unsigned int *)MAINPLLCTL0 |= (((PLLM_val) >> 6) & 0x7f) << 12; /* PLLM[12:6] */
*(unsigned int *)PLL1_PLLM = PLLM_val & 0x3f; /* PLLM[5:0] */
*(unsigned int *)MAINPLLCTL0 |= (((PLLM_val+1)>>1)-1) << 24; /* BWADJ bits */
*(unsigned int *)MAINPLLCTL1 |= 1 << 6;
/*Program BWADJ[7:0] in MAINPLLCTL0*/
/*If necessary program PLLDIV1n. Note that you must aplly the GO operation
to change these dividers to new ratios*/
/*Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
operation is currently in progress*/
// while((*(unsigned int *)PLL1_STAT) & 0x00000001);
/*Program the RATIO field in PLLDIVn to the desired new divide-down rate.
If RATIO field is changed, the PLL controller will flag the change in the
corresponding bit of DCHANGE*/
*(unsigned int *)PLL1_DIV2 = (PLLDIV2_val) | 0x8000; //Set PLLDIV1
*(unsigned int *)PLL1_DIV5 = (PLLDIV5_val) | 0x8000; //Set PLLDIV4
*(unsigned int *)PLL1_DIV8 = (PLLDIV8_val) | 0x8000; //Set PLLDIV7
/*Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
values and align the SYSCLKs as programmed */
*(unsigned int *)PLL1_CMD |= 0x00000001;
i = 2000;
while (i--) {
asm(" NOP");
}
/*In PLLCTL, write PLLRST = 0 to bring PLL out of reset */
ctl = ctl & ~(1<<3);
*(unsigned int *)PLL1_PLLCTL = ctl;
for (i = 0; i < 100; i++) {
j = 2000;
while (j--) {
asm(" NOP");
}
pllstatus = *(unsigned int *)PLL1_STAT;
if ( (pllstatus & 0x1) != 0 )
break;
}
/*Wait for PLL to lock (2000 CLKIN1 cycles) */
secctl = secctl & ~(1<<23);
*(unsigned int *)PLL1_SECCTL = secctl;
/*In PLLCTL, write PLLEN = 1 to enable PLL mode */
ctl = ctl | 0x1;
*(unsigned int *)PLL1_PLLCTL = ctl;
j = 8000;
while (j--) {
asm(" NOP");
}
*(unsigned int *)KICK0 = 0;
*(unsigned int *)KICK1 = 0;
}
volatile int sss=0;
int num=0;
void EDMAtrans(void)
{
int i;
volatile unsigned int *base;
for(i=0; i<512; i++)
{
*(srcBuff1+i) = i+num*256;
}
// *(unsigned int *)CSR &= 0xfffffffe;
// *(unsigned int *)L1DWBAR = (unsigned int)srcBuff1;
// *(unsigned int *)L1DWWC = 512;
// asm( "MFENCE");
// *(unsigned int *)CSR |= 0x00000001;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+DCHMAP);
base[1] = 30<<5;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+PaRAM+0x20*30);
*(base+PaRAMOPT) = 0x00101008;
*(base+PaRAMSRC) = ((unsigned int )srcBuff1) + 0x10000000;
*(base+PaRAMABCNT) = 0x00010100;
*(base+PaRAMDST) = 0x11800800+num*256;
*(base+PaRAMIDX1) = 0x00000000;
*(base+PaRAMRLD) = 0x0000ffff;
*(base+PaRAMCCNT) = 0x00000001;
// base = (unsigned int*)(EDMA3_CC0_BASE+IEVAL);
// *base = 1;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+IESR);
*base |= 1<<1;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+EDMAIER);
*base |= 1<<1;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+EDMAECR);
*base |= 1<<1;
base = (volatile unsigned int*)(EDMA3_CC0_BASE+ESR);
*base |= 1<<1;
//base = (volatile unsigned int*)(EDMA3_CC0_BASE+IPR);
//while(!(*base & 0x2)) {}
}
CSL_CPINTC_Handle hnd;
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj intcObj;
CSL_IntcHandle hTest;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
static void test_isr_handler (void *handler)
{
Uint32 rawStatus;
Uint32 sysIntr = 0;
unsigned int *base;
base = (unsigned int*)(EDMA3_CC0_BASE+EDMAICR);
*base |= 1<<1;
/* Get the RAW status register we read only register 0 as we are interested
* only in System Interrupts 0-31. */
//CSL_CPINTC_getRawInterruptStatus(hnd, 1, &rawStatus);
CSL_CPINTC_clearSysInterrupt(hnd, 36);
sss = 1;
num++;
}
void main(void)
{
volatile unsigned int *base;
unsigned int *p = (unsigned int *)0x0c000000;
int i;
Init_PLL(19, 3-1, 5-1, 64-1);
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
CSL_intcInit(&intcContext);
/* Enable NMIs */
CSL_intcGlobalNmiEnable();
/* Enable global interrupts */
CSL_intcGlobalEnable(&state);
/* Refer to the interrupt architecture and mapping document for the Event ID (INTC0_OUT3)*/
vectId = CSL_INTC_VECTID_12;
hTest = CSL_intcOpen (&intcObj, 63, &vectId , NULL);
/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = &test_isr_handler;
EventRecord.arg = 0;
CSL_intcPlugEventHandler(hTest,&EventRecord);
/* Enabling the events. */
CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL);
base = (volatile unsigned int *)(INTC0_BASE+HINT_GBL_EN);
*base = 0;
asm( " NOP 9");
// Map the input system event to a channel.
base = (volatile unsigned int *)(INTC0_BASE+SINT_CHL_MAP);
base[9] = (base[9]&0xffffff00)+0x00003;
asm( " NOP 9");
// Enable the system interrupt
base = (volatile unsigned int *)(INTC0_BASE+SINT_EN_IDX_SET);
*base = 36;
asm( " NOP 9");
// Enable the channel (output).
base = (volatile unsigned int *)(INTC0_BASE+HINT_EN_IDX_SET);
*base = 3;
asm( " NOP 9");
// Enable all host interrupts.
base = (volatile unsigned int *)(INTC0_BASE+HINT_GBL_EN);
*base |= 1;
asm( " NOP 9");
i = 0;
sss = 1;
while(i<10)
{
if(sss==1)
{
EDMAtrans();
i++;
sss = 0;
}
}
while(1) {}
}
