TDA4VM-Q1: capture block at dequeue

xie jc

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Tool/software:

Hi, TI experts,

SDK version: 10.1

We write an demo:　(1920x1280@30fps UYVY)capture -> ldc -> msc -> msc -> csitx(1280x720@30fps RGB888), this simple demo can run for the whole night(more than 12hours)

but when all our business function applications are running, there is a relatively high probability that the dequeue function at the capture node will get stuck.

Our questions are as follows:

Is there any way to troubleshoot this problem? We are worried that it is caused by DDR resource contention.
Is there a way to increase the DDR priority of the capture node, such as through udma?

BRs

regard

5 months ago

0 Brijesh Jadav 5 months ago

TI__Guru**** 476235 points

Hi jc,

Are you seeing this issue on TDA4VM? As such CSIRX has been given the highest priority, so high DDR load should not have affected, are you sure that the SERDES and camera was still streaming when this issue happened? Also can we please get the performance statistics to figure out if the capture is still running and is dropping all the frame due to some other issue?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Thanks for your quick reply.

I think the SERDES and camera were still streaming when this issue happened, because CsirxDrv_udmaCQEventCb is called normally.

How to add perfomance statistics code?

BRs

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Yes, this issue is happened on TDA4VM

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

If this CSirxDrv_udmaCqEvent is getting called, that means capture is working. Some part of the your video chain has stopped and so entire chain has stopped,

Regarding statistics. can you please refer to vision apps demo? In vision apps demos, when we press 'p', it prints the performance statistics on the console.

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Please refer to below pictures.

ng.txt

BRs

0 xie jc 5 months ago in reply to xie jc

Expert 2180 points

Hi, Brijesh,

When the issue occuring, there is no error reported, and the Queue count and Dequeue Count also seems normally, but capture node can not deque buffer.

BRs

0 xie jc 5 months ago in reply to xie jc

Expert 2180 points

Hi, Brijesh:

Is there any quick way to recover from this abnormal state?

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

but there is absolutely no error from the capture. In all the prints, i don't see any error from capture, no CRC/ECC/overflow errors. The only change is incrementing dropped frames, it is continuously dropping the frame, most likely it has run out of output buffers and that means

- one of the component in the chain is not working and because of which entire graph is stopped running, but capture would still be running and dropping the frame.

- or somehow node is not giving back the buffers to the driver and so its dropping all the buffers and then when node is calling dequeue, it will hang.

Are you using capture output as graph parameters? Then are you sharing capture output with some other component? Can you please make sure that this component is returning the buffers correctly to the application?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Our graph link: capture -> ldc , we shared ldc buffer to other application

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

In the attached screen shot, i dont see capture or ldc output buffer shared with the other component. Both graph parameters are dequeued and just enqueued back. This should not have caused any issue. Is it possible to just run this graph without sharing ldc output with the other component?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

I want to show all dequeue and queue func in one screen shot, so I remove the "sharing ldc phy addr part", we just send ldc buffer phy addr to a middle software, and will not wait for response.

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

Yes, looking at the code, there is no waiting and dequeued buffer is enqueued back to the LDC node. Here is capture output also used as graph parameter? Is it possible to remove capture output as graph parameters and just use LDC output as graph parameter and see if it helps?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

We did below tests:
1. cam app: rm LDC node and sharing addr part, other apps using camera buffer change to read pic instead of using camera buffer. --- test for whole night and problems not occured (camera graph frame rate can up to 30fps and keep stable)

2. cam app: keep LDC and capture node and rm sharing addr part, other apps using camera buffer change to read pic instead of using camera buffer --- easy to reproduce problem

BRs

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Brijesh Jadav said:
Is it possible to remove capture output as graph parameters and just use LDC output as graph parameter and see if it helps?

Hi, Brijesh,

We will try this

0 xie jc 5 months ago in reply to xie jc

Expert 2180 points

reproduce again

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

Is it possible to share this part of the code for the review?

This is because just by adding LDC to the graph should have cause error in capture, even if there are two graph parameters..

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Brijesh Jadav said:
Is it possible to share this part of the code for the review?

Hi, Brijesh,

Sure, can you send me your email address in private?

BRs

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

I asked one of your colleagues, Joe.Shen, to help forward it. He should forward it to you later.

BRs

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Thanks xie jc, i will review and get back to you by next week.

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Ok, copy that.

BRs

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

As we discussed in the call today, lets first check if the issue is coming due to LDC. So when the issue occurs, can we please dump 8 registers from the offset 0x2c010000 and share them?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

I try to read 0x2c010000, but the system reported an error, is this register readable on A72?

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

This is correct address, as per file source/drivers/hw_include/j722s/cslr_soc_baseaddress.h, macro, CSL_VPAC0_IVPAC_TOP_0_CFG_SLV_HTS_S_VBUSP_BASE, is set to 0x2c010000, so it should be accessible.

Did you try reading this register after R5F is booted?

Also is it possible to check this register value from R5F, maybe using JTAG+CCS?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

the SoC on our board is TDA4VM

should i read: #define CSL_VPAC0_HTS_S_VBUSP_BASE (0xf008000UL)

0 xie jc 5 months ago in reply to xie jc

Expert 2180 points

Hi, Brijesh,

I read 0xf008000 - 0xf00802C when the block occrur

Fullscreen readldc.txt Download

devmem2 0xf008000
em2 0xf008024
devmem2 0xf008028
devmem2 0xf00802C/dev/mem opened.
Memory mapped at address 0xffff83625000.
Read at address  0x0F008000 (0xffff83625000): 0x00000000
root@j721e-evm:~# devmem2 0xf008004
/dev/mem opened.
Memory mapped at address 0xffffa61fc000.
Read at address  0x0F008004 (0xffffa61fc004): 0x00000001
root@j721e-evm:~# devmem2 0xf008008
/dev/mem opened.
Memory mapped at address 0xffff88e8c000.
Read at address  0x0F008008 (0xffff88e8c008): 0x00000000
root@j721e-evm:~# devmem2 0xf00800C
/dev/mem opened.
Memory mapped at address 0xffffb542c000.
Read at address  0x0F00800C (0xffffb542c00c): 0x00000000
root@j721e-evm:~# devmem2 0xf008010
/dev/mem opened.
Memory mapped at address 0xffffb02b2000.
Read at address  0x0F008010 (0xffffb02b2010): 0x00000000
root@j721e-evm:~# devmem2 0xf008014
/dev/mem opened.
Memory mapped at address 0xffffbc8ff000.
Read at address  0x0F008014 (0xffffbc8ff014): 0x00000000
root@j721e-evm:~# devmem2 0xf008018
/dev/mem opened.
Memory mapped at address 0xffff87b52000.
Read at address  0x0F008018 (0xffff87b52018): 0x00000000
root@j721e-evm:~# devmem2 0xf00801C
/dev/mem opened.
Memory mapped at address 0xffffb21e2000.
Read at address  0x0F00801C (0xffffb21e201c): 0x00000000
root@j721e-evm:~# devmem2 0xf008020
/dev/mem opened.
Memory mapped at address 0xffff8ea36000.
Read at address  0x0F008020 (0xffff8ea36020): 0x00000000
root@j721e-evm:~# devmem2 0xf008024
/dev/mem opened.
Memory mapped at address 0xffff86c86000.
Read at address  0x0F008024 (0xffff86c86024): 0x00000000
root@j721e-evm:~# devmem2 0xf008028
/dev/mem opened.
Memory mapped at address 0xffffbea19000.
Read at address  0x0F008028 (0xffffbea19028): 0x00000000

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

this is strange, LDC has hung up, because of this, entire pipeline has stopped. Do you still have this setup? Is it possible to share LDC registers and also LDC LUT when this issue occurs? We might need to dump registers multiple times, so is it possible to have setup ready with the stall condition?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

We still have the reproduction environment, and this issue is relatively easy to reproduce. Could you specify which registers need to be read, or provide the detailed steps to do so?

BRs

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

When the issue occurs, it gets stuck during the 'dequeue capture node buffer' operation. Could it be that after the stall, the pipeline is completely halted, causing the LDC registers to read as abnormal when we try to dump them?

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

no, its the other way, since LDC is stuck, capture will eventually run out of the buffers and will start dropping all the frame and this is why dequeue operation for capture will also get stuck..

We need to figure out why LDC is getting stuck..

Can you please dump 128 registers from 0xF0020000 offset? This contains LDC configuration, lets see if this is set to correct values.

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
no, its the other way, since LDC is stuck, capture will eventually run out of the buffers and will start dropping all the frame and this is why dequeue operation for capture will also get stuck..

That makes sense.

Brijesh Jadav said:
0xF0020000 offset

Did you mean this register? #define CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE (0xf020000UL)

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
Can you please dump 128 registers from 0xF0020000 offset? This contains LDC configuration, lets see if this is set to correct values.

I read these registers when issuse occur

Fullscreen readldc1.txt Download

RAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389


root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

./test.sh
Reading 128 registers starting from 0xF020000...
--------------------------------------------------
/dev/mem opened.
Memory mapped at address 0xffffbbc75000.
Read at address  0x0F020000 (0xffffbbc75000): 0x64C60000
/dev/mem opened.
Memory mapped at address 0xffffbf48f000.
Read at address  0x0F020004 (0xffffbf48f004): 0x000A1E2A
/dev/mem opened.
Memory mapped at address 0xffffb3292000.
Read at address  0x0F020008 (0xffffb3292008): 0x00000805
/dev/mem opened.
Memory mapped at address 0xffffbe3c9000.
Read at address  0x0F02000C (0xffffbe3c900c): 0x00000040
/dev/mem opened.
Memory mapped at address 0xffffaab96000.
Read at address  0x0F020010 (0xffffaab96010): 0x00000002
/dev/mem opened.
Memory mapped at address 0xffffb2a90000.
Read at address  0x0F020014 (0xffffb2a90014): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaad6f000.
Read at address  0x0F020018 (0xffffaad6f018): 0x05000780
/dev/mem opened.
Memory mapped at address 0xffff954ee000.
Read at address  0x0F02001C (0xffff954ee01c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa5dc8000.
Read at address  0x0F020020 (0xffffa5dc8020): 0x05000780
/dev/mem opened.
Memory mapped at address 0xffffa8f21000.
Read at address  0x0F020024 (0xffffa8f21024): 0x00004040
/dev/mem opened.
Memory mapped at address 0xffffbb464000.
Read at address  0x0F020028 (0xffffbb464028): 0x00001000
/dev/mem opened.
Memory mapped at address 0xffffb2c5d000.
Read at address  0x0F02002C (0xffffb2c5d02c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa0489000.
Read at address  0x0F020030 (0xffffa0489030): 0x00001000
/dev/mem opened.
Memory mapped at address 0xffff96112000.
Read at address  0x0F020034 (0xffff96112034): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff97f99000.
Read at address  0x0F020038 (0xffff97f99038): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbc681000.
Read at address  0x0F02003C (0xffffbc68103c): 0x00000000
GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

/dev/mem opened.
Memory mapped at address 0xffff99408000.
Read at address  0x0F020040 (0xffff99408040): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb4804000.
Read at address  0x0F020044 (0xffffb4804044): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb78f0000.
Read at address  0x0F020048 (0xffffb78f0048): 0xBB392000
/dev/mem opened.
Memory mapped at address 0xffff88351000.
Read at address  0x0F02004C (0xffff8835104c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8a280000.
Read at address  0x0F020050 (0xffff8a280050): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9da25000.
Read at address  0x0F020054 (0xffff9da25054): 0x00000F00
/dev/mem opened.
Memory mapped at address 0xffffa40fc000.
Read at address  0x0F020058 (0xffffa40fc058): 0x000000FA
/dev/mem opened.
Memory mapped at address 0xffffb240c000.
Read at address  0x0F02005C (0xffffb240c05c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9b188000.
Read at address  0x0F020060 (0xffff9b188060): 0x01180118
/dev/mem opened.
Memory mapped at address 0xffffb5ecc000.
Read at address  0x0F020064 (0xffffb5ecc064): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff96084000.
Read at address  0x0F020068 (0xffff96084068): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff87f64000.
Read at address  0x0F02006C (0xffff87f6406c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff80656000.
Read at address  0x0F020070 (0xffff80656070): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9255b000.
Read at address  0x0F020074 (0xffff9255b074): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb0eb0000.
Read at address  0x0F020078 (0xffffb0eb0078): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbd608000.
Read at address  0x0F02007C (0xffffbd60807c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff80a26000.
Read at address  0x0F020080 (0xffff80a26080): 0x00000780
/dev/mem opened.
Memory mapped at address 0xffff9104b000.
Read at address  0x0F020084 (0xffff9104b084): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8cf77000.
Read at address  0x0F020088 (0xffff8cf77088): 0x00000500
/dev/mem opened.
Memory mapped at address 0xffff898d4000.
Read at address  0x0F02008C (0xffff898d408c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff97522000.
Read at address  0x0F020090 (0xffff97522090): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa14b3000.
Read at address  0x0F020094 (0xffffa14b3094): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8b095000.
Read at address  0x0F020098 (0xffff8b095098): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffac611000.
Read at address  0x0F02009C (0xffffac61109c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaf0b7000.
Read at address  0x0F0200A0 (0xffffaf0b70a0): 0x00000000
GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

/dev/mem opened.
Memory mapped at address 0xffffbdff6000.
Read at address  0x0F0200A4 (0xffffbdff60a4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa7574000.
Read at address  0x0F0200A8 (0xffffa75740a8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa2de1000.
Read at address  0x0F0200AC (0xffffa2de10ac): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffae50b000.
Read at address  0x0F0200B0 (0xffffae50b0b0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffab88d000.
Read at address  0x0F0200B4 (0xffffab88d0b4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9b136000.
Read at address  0x0F0200B8 (0xffff9b1360b8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8c021000.
Read at address  0x0F0200BC (0xffff8c0210bc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb95e1000.
Read at address  0x0F0200C0 (0xffffb95e10c0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff85e85000.
Read at address  0x0F0200C4 (0xffff85e850c4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff84aaa000.
Read at address  0x0F0200C8 (0xffff84aaa0c8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffba913000.
Read at address  0x0F0200CC (0xffffba9130cc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff86b68000.
Read at address  0x0F0200D0 (0xffff86b680d0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8e55d000.
Read at address  0x0F0200D4 (0xffff8e55d0d4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb4bf3000.
Read at address  0x0F0200D8 (0xffffb4bf30d8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbef07000.
Read at address  0x0F0200DC (0xffffbef070dc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff90c9e000.
Read at address  0x0F0200E0 (0xffff90c9e0e0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb9005000.
Read at address  0x0F0200E4 (0xffffb90050e4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa539b000.
Read at address  0x0F0200E8 (0xffffa539b0e8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa64b2000.
Read at address  0x0F0200EC (0xffffa64b20ec): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffba3ce000.
Read at address  0x0F0200F0 (0xffffba3ce0f0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb5018000.
Read at address  0x0F0200F4 (0xffffb50180f4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa34b1000.
Read at address  0x0F0200F8 (0xffffa34b10f8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaf9b1000.
Read at address  0x0F0200FC (0xffffaf9b10fc): 0x00000000
GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

/dev/mem opened.
Memory mapped at address 0xffff923d8000.
Read at address  0x0F020100 (0xffff923d8100): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8c062000.
Read at address  0x0F020104 (0xffff8c062104): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb2cdf000.
Read at address  0x0F020108 (0xffffb2cdf108): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff822af000.
Read at address  0x0F02010C (0xffff822af10c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa07fe000.
Read at address  0x0F020110 (0xffffa07fe110): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa213a000.
Read at address  0x0F020114 (0xffffa213a114): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff94e02000.
Read at address  0x0F020118 (0xffff94e02118): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff92f89000.
Read at address  0x0F02011C (0xffff92f8911c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa8b10000.
Read at address  0x0F020120 (0xffffa8b10120): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff99fa5000.
Read at address  0x0F020124 (0xffff99fa5124): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff83384000.
Read at address  0x0F020128 (0xffff83384128): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9d03a000.
Read at address  0x0F02012C (0xffff9d03a12c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff91862000.
Read at address  0x0F020130 (0xffff91862130): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8c219000.
Read at address  0x0F020134 (0xffff8c219134): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff97498000.
Read at address  0x0F020138 (0xffff97498138): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb4fc7000.
Read at address  0x0F02013C (0xffffb4fc713c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff91b70000.
Read at address  0x0F020140 (0xffff91b70140): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8456e000.
Read at address  0x0F020144 (0xffff8456e144): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaba70000.
Read at address  0x0F020148 (0xffffaba70148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff97e43000.
Read at address  0x0F02014C (0xffff97e4314c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb4a4e000.
Read at address  0x0F020150 (0xffffb4a4e150): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa73b5000.
Read at address  0x0F020154 (0xffffa73b5154): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbe8f0000.
Read at address  0x0F020158 (0xffffbe8f0158): 0x00000000
GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

/dev/mem opened.
Memory mapped at address 0xffffad5a7000.
Read at address  0x0F02015C (0xffffad5a715c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff99b31000.
Read at address  0x0F020160 (0xffff99b31160): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8e2fa000.
Read at address  0x0F020164 (0xffff8e2fa164): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff85dac000.
Read at address  0x0F020168 (0xffff85dac168): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaa0ea000.
Read at address  0x0F02016C (0xffffaa0ea16c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa88e7000.
Read at address  0x0F020170 (0xffffa88e7170): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb73b1000.
Read at address  0x0F020174 (0xffffb73b1174): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaebf5000.
Read at address  0x0F020178 (0xffffaebf5178): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffac694000.
Read at address  0x0F02017C (0xffffac69417c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa5f7c000.
Read at address  0x0F020180 (0xffffa5f7c180): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff86aa5000.
Read at address  0x0F020184 (0xffff86aa5184): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff99e35000.
Read at address  0x0F020188 (0xffff99e35188): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffaa8ad000.
Read at address  0x0F02018C (0xffffaa8ad18c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb5519000.
Read at address  0x0F020190 (0xffffb5519190): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa5db5000.
Read at address  0x0F020194 (0xffffa5db5194): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff8fc7a000.
Read at address  0x0F020198 (0xffff8fc7a198): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9cb43000.
Read at address  0x0F02019C (0xffff9cb4319c): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff967e3000.
Read at address  0x0F0201A0 (0xffff967e31a0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffab84c000.
Read at address  0x0F0201A4 (0xffffab84c1a4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9bafc000.
Read at address  0x0F0201A8 (0xffff9bafc1a8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa59c8000.
Read at address  0x0F0201AC (0xffffa59c81ac): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb3717000.
Read at address  0x0F0201B0 (0xffffb37171b0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff88a80000.
Read at address  0x0F0201B4 (0xffff88a801b4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff95d65000.
Read at address  0x0F0201B8 (0xffff95d651b8): 0x00000000
GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

/dev/mem opened.
Memory mapped at address 0xffffa0531000.
Read at address  0x0F0201BC (0xffffa05311bc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa16ef000.
Read at address  0x0F0201C0 (0xffffa16ef1c0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa1088000.
Read at address  0x0F0201C4 (0xffffa10881c4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbe760000.
Read at address  0x0F0201C8 (0xffffbe7601c8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb6f14000.
Read at address  0x0F0201CC (0xffffb6f141cc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa1b09000.
Read at address  0x0F0201D0 (0xffffa1b091d0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9f6ce000.
Read at address  0x0F0201D4 (0xffff9f6ce1d4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9d482000.
Read at address  0x0F0201D8 (0xffff9d4821d8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffa4292000.
Read at address  0x0F0201DC (0xffffa42921dc): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffb9183000.
Read at address  0x0F0201E0 (0xffffb91831e0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9db71000.
Read at address  0x0F0201E4 (0xffff9db711e4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffacaaf000.
Read at address  0x0F0201E8 (0xffffacaaf1e8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffae4b7000.
Read at address  0x0F0201EC (0xffffae4b71ec): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff9afaa000.
Read at address  0x0F0201F0 (0xffff9afaa1f0): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff86b2f000.
Read at address  0x0F0201F4 (0xffff86b2f1f4): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff829e8000.
Read at address  0x0F0201F8 (0xffff829e81f8): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffff93584000.
Read at address  0x0F0201FC (0xffff935841fc): 0x00000000
--------------------------------------------------
Register dump completed.
root@j721e-evm:~# GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

GRAPH:   OpenVxBevGraph (#nodes =   8, #executions =   1454)
 NODE:          MPU-0:     tivxVirtualCameraode: avg =  38109 usecs, min/max =  10904 / 295437 usecs, #executions =       1454
 NODE:          MPU-0:     tivxImageMattingNode: avg =  12019 usecs, min/max =   1043 /  48747 usecs, #executions =       1454
 NODE:          DSP-1:              PreProcNode: avg =   4199 usecs, min/max =   1661 /  16965 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  28690 usecs, min/max =  21399 /  30451 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   5312 usecs, min/max =   3481 /  10011 usecs, #executions =       1454
 NODE:          DSP-1:    tivxViewTransformNode: avg = 182740 usecs, min/max = 117443 / 231305 usecs, #executions =       1454
 NODE:       DSP_C7-1:                tidl_node: avg =  46137 usecs, min/max =  37494 /  51685 usecs, #executions =       1454
 NODE:          DSP-1:      tivxSaveTensorsNode: avg =   3111 usecs, min/max =    366 /   4075 usecs, #executions =       1454

GRAPH: OpenVxCaptureGraph (#nodes =   2, #executions =  10389)
 NODE:       CAPTURE2:              CaptureNode: avg =  13307 usecs, min/max =    154 / 499937 usecs, #executions =      10389
 NODE:      VPAC_LDC1:                 ldc_node: avg =  21294 usecs, min/max =  16093 /  45192 usecs, #executions =      10389

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

ok, let me review the register settings and get back to you.

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Ok, thanks

0 Brijesh Jadav 5 months ago in reply to Brijesh Jadav

TI__Guru**** 476235 points

Hi xie jc,

Looking at the register dump, i see you are using LDC for YUV422 to YUV422 format and back-mapping is disabled, which means LDC is not really doing anything.. It just reads the YUV422 data and writes it out in YUV422 format, can you please confirm this? This shouldn't have caused stall in LDC.

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

You are right, We only use it for format conversion.

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Apologies for the delay in responding— I was off work yesterday.

0 Brijesh Jadav 5 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

But in this case, LDC can get stalled only if the memory is inaccessible. I see that input buffer location is 0xBB392000 in the register. Is this accessible memory? Can you try accessing this memory from CCS/Linux?

For the output address, we would probably have to print the output address, because it is programmed in the DMA engine.

Is it possible to have debug session to check all LDC parameters?

Regards,

Brijesh

0 xie jc 5 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
0xBB392000 in the register. Is this accessible memory?

this is accessible memory, you can refer the system map html file we are using now

Fullscreen system_memory_map.html.txt Download

<!DOCTYPE html>
<html>
<style type="text/css">
.tg  {border-collapse:collapse;border-spacing:0;border-color:#999;}
.tg td{font-family:Arial, sans-serif;font-size:14px;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#444;background-color:#F7FDFA;}
.tg th{font-family:Arial, sans-serif;font-size:14px;font-weight:normal;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#fff;background-color:#26ADE4;}
.tg .tg-kftd{background-color:#efefef;text-align:left;vertical-align:top}
.tg .tg-6sgx{background-color:#ffffff;text-align:left;vertical-align:top}
.tg .tg-fjir{background-color:#343434;color:#ffffff;text-align:left;vertical-align:top}
</style>

    <head>
        <title>System Memory Map for Linux+RTOS mode</title>
    </head>
    <body>
        <h1>System Memory Map for Linux+RTOS mode</h1>
        <p>Note, this file is auto generated using PyTI_PSDK_RTOS tool</p>
        <table class="tg">
            <tr>
                <th class="tg-fjir">Name</th>
                <th class="tg-fjir">Start Addr</th>
                <th class="tg-fjir">End Addr</th>
                <th class="tg-fjir">Size </th>
                <th class="tg-fjir">Attributes</th>
                <th class="tg-fjir">Description</th>
            </tr>
            <tr>
                <td class="tg-kftd">L2RAM_C66x_1</td>
                <td class="tg-kftd">0x00800000</td>
                <td class="tg-kftd">0x00837FFF</td>
                <td class="tg-kftd">224.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">L2 for C66x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">L2RAM_C66x_2</td>
                <td class="tg-6sgx">0x00800000</td>
                <td class="tg-6sgx">0x00837FFF</td>
                <td class="tg-6sgx">224.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">L2 for C66x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">MAIN_OCRAM_MCU2_0</td>
                <td class="tg-kftd">0x03600000</td>
                <td class="tg-kftd">0x0363FFFF</td>
                <td class="tg-kftd">256.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Main OCRAM for MCU2_0</td>
            </tr>
            <tr>
                <td class="tg-6sgx">MAIN_OCRAM_MCU2_1</td>
                <td class="tg-6sgx">0x03640000</td>
                <td class="tg-6sgx">0x0367FFFF</td>
                <td class="tg-6sgx">256.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Main OCRAM for MCU2_1</td>
            </tr>
            <tr>
                <td class="tg-kftd">L2RAM_C7x_1</td>
                <td class="tg-kftd">0x64800000</td>
                <td class="tg-kftd">0x6486FFFF</td>
                <td class="tg-kftd">448.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">L2 for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">L1RAM_C7x_1</td>
                <td class="tg-6sgx">0x64E00000</td>
                <td class="tg-6sgx">0x64E03FFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">L1 for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-kftd">MSMC_MPU1</td>
                <td class="tg-kftd">0x70000000</td>
                <td class="tg-kftd">0x7001FFFF</td>
                <td class="tg-kftd">128.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">MSMC reserved for MPU1 for ATF</td>
            </tr>
            <tr>
                <td class="tg-6sgx">MSMC_C7x_1</td>
                <td class="tg-6sgx">0x70020000</td>
                <td class="tg-6sgx">0x706ECFFF</td>
                <td class="tg-6sgx"> 6.80 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">MSMC for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-kftd">MSMC_MCU3_0</td>
                <td class="tg-kftd">0x706ED000</td>
                <td class="tg-kftd">0x707E7FFF</td>
                <td class="tg-kftd">1004.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">MSMC for MCU3_0</td>
            </tr>
            <tr>
                <td class="tg-6sgx">MSMC_DMSC</td>
                <td class="tg-6sgx">0x707F0000</td>
                <td class="tg-6sgx">0x707FFFFF</td>
                <td class="tg-6sgx">64.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">MSMC reserved for DMSC IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_0_IPC</td>
                <td class="tg-kftd">0xA0000000</td>
                <td class="tg-kftd">0xA00FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_0 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_0_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA0100000</td>
                <td class="tg-6sgx">0xA01003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_0 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_0</td>
                <td class="tg-kftd">0xA0100400</td>
                <td class="tg-kftd">0xA0FFFFFF</td>
                <td class="tg-kftd">15.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_0 for code/data</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_1_IPC</td>
                <td class="tg-6sgx">0xA1000000</td>
                <td class="tg-6sgx">0xA10FFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_1_RESOURCE_TABLE</td>
                <td class="tg-kftd">0xA1100000</td>
                <td class="tg-kftd">0xA11003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_1</td>
                <td class="tg-6sgx">0xA1100400</td>
                <td class="tg-6sgx">0xA1FFFFFF</td>
                <td class="tg-6sgx">15.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0_IPC</td>
                <td class="tg-kftd">0xA2000000</td>
                <td class="tg-kftd">0xA20FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_0 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_0_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA2100000</td>
                <td class="tg-6sgx">0xA21003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_0 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0</td>
                <td class="tg-kftd">0xA2100400</td>
                <td class="tg-kftd">0xA3FFFFFF</td>
                <td class="tg-kftd">31.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_0 for code/data</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_1_IPC</td>
                <td class="tg-6sgx">0xA4000000</td>
                <td class="tg-6sgx">0xA40FFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_1_RESOURCE_TABLE</td>
                <td class="tg-kftd">0xA4100000</td>
                <td class="tg-kftd">0xA41003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_1</td>
                <td class="tg-6sgx">0xA4100400</td>
                <td class="tg-6sgx">0xA5FFFFFF</td>
                <td class="tg-6sgx">31.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU3_0_IPC</td>
                <td class="tg-kftd">0xA6000000</td>
                <td class="tg-kftd">0xA60FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU3_0 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU3_0_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA6100000</td>
                <td class="tg-6sgx">0xA61003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU3_0 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU3_0</td>
                <td class="tg-kftd">0xA6100400</td>
                <td class="tg-kftd">0xA6FFFFFF</td>
                <td class="tg-kftd">15.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU3_0 for code/data</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU3_1_IPC</td>
                <td class="tg-6sgx">0xA7000000</td>
                <td class="tg-6sgx">0xA70FFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU3_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU3_1_RESOURCE_TABLE</td>
                <td class="tg-kftd">0xA7100000</td>
                <td class="tg-kftd">0xA71003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU3_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU3_1</td>
                <td class="tg-6sgx">0xA7100400</td>
                <td class="tg-6sgx">0xA7FFFFFF</td>
                <td class="tg-6sgx">15.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU3_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66x_2_IPC</td>
                <td class="tg-kftd">0xA8000000</td>
                <td class="tg-kftd">0xA80FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C66x_2 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66x_1_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA8100000</td>
                <td class="tg-6sgx">0xA81003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C66x_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66x_1_BOOT</td>
                <td class="tg-kftd">0xA8200000</td>
                <td class="tg-kftd">0xA82003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C66x_1 for boot section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66x_1</td>
                <td class="tg-6sgx">0xA8200400</td>
                <td class="tg-6sgx">0xA8FFFFFF</td>
                <td class="tg-6sgx">14.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C66x_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66x_1_IPC</td>
                <td class="tg-kftd">0xA9000000</td>
                <td class="tg-kftd">0xA90FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C66x_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66x_2_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA9100000</td>
                <td class="tg-6sgx">0xA91003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C66x_2 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66x_2_BOOT</td>
                <td class="tg-kftd">0xA9200000</td>
                <td class="tg-kftd">0xA92003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C66x_2 for boot section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66x_2</td>
                <td class="tg-6sgx">0xA9200400</td>
                <td class="tg-6sgx">0xA9FFFFFF</td>
                <td class="tg-6sgx">14.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C66x_2 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">IPC_VRING_MEM</td>
                <td class="tg-kftd">0xAA000000</td>
                <td class="tg-kftd">0xABFFFFFF</td>
                <td class="tg-kftd">32.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for IPC Vring's. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">APP_LOG_MEM</td>
                <td class="tg-6sgx">0xAC000000</td>
                <td class="tg-6sgx">0xAC03FFFF</td>
                <td class="tg-6sgx">256.00 KB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for remote core logging</td>
            </tr>
            <tr>
                <td class="tg-kftd">TIOVX_OBJ_DESC_MEM</td>
                <td class="tg-kftd">0xAC040000</td>
                <td class="tg-kftd">0xAFFFFFFF</td>
                <td class="tg-kftd">63.75 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">APP_FILEIO_MEM</td>
                <td class="tg-6sgx">0xB0000000</td>
                <td class="tg-6sgx">0xB03FFFFF</td>
                <td class="tg-6sgx"> 4.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for remote core file operations</td>
            </tr>
            <tr>
                <td class="tg-kftd">TIOVX_LOG_RT_MEM</td>
                <td class="tg-kftd">0xB0400000</td>
                <td class="tg-kftd">0xB1FFFFFF</td>
                <td class="tg-kftd">28.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_IPC</td>
                <td class="tg-6sgx">0xB2000000</td>
                <td class="tg-6sgx">0xB20FFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1_RESOURCE_TABLE</td>
                <td class="tg-kftd">0xB2100000</td>
                <td class="tg-kftd">0xB21003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_BOOT</td>
                <td class="tg-6sgx">0xB2200000</td>
                <td class="tg-6sgx">0xB22003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for boot section</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1_VECS</td>
                <td class="tg-kftd">0xB2400000</td>
                <td class="tg-kftd">0xB2403FFF</td>
                <td class="tg-kftd">16.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for vecs section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_SECURE_VECS</td>
                <td class="tg-6sgx">0xB2600000</td>
                <td class="tg-6sgx">0xB2603FFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for secure vecs section</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1</td>
                <td class="tg-kftd">0xB2604000</td>
                <td class="tg-kftd">0xB7FFFFFF</td>
                <td class="tg-kftd">89.98 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_SHARED_MEM</td>
                <td class="tg-6sgx">0xB8000000</td>
                <td class="tg-6sgx">0xED1FFFFF</td>
                <td class="tg-6sgx">850.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for shared memory buffers in DDR</td>
            </tr>
            <tr>
                <td class="tg-kftd">MCU2_0_LOG_MEM</td>
                <td class="tg-kftd">0xED200000</td>
                <td class="tg-kftd">0xED9FFFFF</td>
                <td class="tg-kftd"> 8.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">shared Memory for MCU2_0 LOG Debug</td>
            </tr>
            <tr>
                <td class="tg-6sgx">MVLOG_MEM</td>
                <td class="tg-6sgx">0xEDA00000</td>
                <td class="tg-6sgx">0xEE1FFFFF</td>
                <td class="tg-6sgx"> 8.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">shared Memory for MCU3_0 LOG Debug</td>
            </tr>
            <tr>
                <td class="tg-kftd">SHMIPC_VRING_MEM</td>
                <td class="tg-kftd">0xEE200000</td>
                <td class="tg-kftd">0xF01FFFFF</td>
                <td class="tg-kftd">32.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">shared Memory for SHMIPC Vring's</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_0_LOCAL_HEAP</td>
                <td class="tg-6sgx">0xF0200000</td>
                <td class="tg-6sgx">0xF09FFFFF</td>
                <td class="tg-6sgx"> 8.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_0 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_1_LOCAL_HEAP</td>
                <td class="tg-kftd">0xF0A00000</td>
                <td class="tg-kftd">0xF11FFFFF</td>
                <td class="tg-kftd"> 8.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_0_LOCAL_HEAP</td>
                <td class="tg-6sgx">0xF1200000</td>
                <td class="tg-6sgx">0xF13FFFFF</td>
                <td class="tg-6sgx"> 2.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_0 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0_VISS_CONFIG_HEAP</td>
                <td class="tg-kftd">0xF1400000</td>
                <td class="tg-kftd">0xF14FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">VISS configuration memory. MUST be write through cache policy.</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_1_LOCAL_HEAP</td>
                <td class="tg-6sgx">0xF1500000</td>
                <td class="tg-6sgx">0xF16FFFFF</td>
                <td class="tg-6sgx"> 2.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU3_0_LOCAL_HEAP</td>
                <td class="tg-kftd">0xF1700000</td>
                <td class="tg-kftd">0xF1EFFFFF</td>
                <td class="tg-kftd"> 8.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU3_0 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU3_1_LOCAL_HEAP</td>
                <td class="tg-6sgx">0xF1F00000</td>
                <td class="tg-6sgx">0xF1FFFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU3_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66X_1_LOCAL_HEAP</td>
                <td class="tg-kftd">0xF2000000</td>
                <td class="tg-kftd">0xF2FFFFFF</td>
                <td class="tg-kftd">16.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c66x_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66X_1_SCRATCH</td>
                <td class="tg-6sgx">0xF3000000</td>
                <td class="tg-6sgx">0xF3FFFFFF</td>
                <td class="tg-6sgx">16.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c66x_1 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C66X_2_LOCAL_HEAP</td>
                <td class="tg-kftd">0xF4000000</td>
                <td class="tg-kftd">0xF4FFFFFF</td>
                <td class="tg-kftd">16.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c66x_2 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C66X_2_SCRATCH</td>
                <td class="tg-6sgx">0xF5000000</td>
                <td class="tg-6sgx">0xF5FFFFFF</td>
                <td class="tg-6sgx">16.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c66x_2 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">INTERCORE_ETH_DESC_MEM</td>
                <td class="tg-kftd">0xF6000000</td>
                <td class="tg-kftd">0xF67FFFFF</td>
                <td class="tg-kftd"> 8.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Inter-core ethernet shared desc queues. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">INTERCORE_ETH_DATA_MEM</td>
                <td class="tg-6sgx">0xF6800000</td>
                <td class="tg-6sgx">0xF7FFFFFF</td>
                <td class="tg-6sgx">24.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Inter-core ethernet shared data buffers. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-kftd">UpdateRxFifo</td>
                <td class="tg-kftd">0xFB100400</td>
                <td class="tg-kftd">0xFB1023FF</td>
                <td class="tg-kftd"> 8.00 KB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">ddr-update-rx-fifo-region-memories</td>
            </tr>
            <tr>
                <td class="tg-6sgx">UpdateTxFifo</td>
                <td class="tg-6sgx">0xFB102400</td>
                <td class="tg-6sgx">0xFB1043FF</td>
                <td class="tg-6sgx"> 8.00 KB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">ddr-update-tx-fifo-region-memories</td>
            </tr>
            <tr>
                <td class="tg-kftd">Update_Norflash_SHM</td>
                <td class="tg-kftd">0xFB200400</td>
                <td class="tg-kftd">0xFBE003FF</td>
                <td class="tg-kftd">12.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">ddr_update_norflash_shm_addr_memories</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_1_SCRATCH</td>
                <td class="tg-6sgx">0x100000000</td>
                <td class="tg-6sgx">0x1043FFFFF</td>
                <td class="tg-6sgx">68.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c7x_1 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP</td>
                <td class="tg-kftd">0x104400000</td>
                <td class="tg-kftd">0x1143FFFFF</td>
                <td class="tg-kftd">256.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c7x_1 for local heap</td>
            </tr>
        </table>
    </body>
</html>

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

I add some log in vx_target.c, as you said, block in func ownTargetNodeDescNodeExecuteKernel when proccess LDC node

BRs

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Brijesh Jadav said:
For the output address, we would probably have to print the output address, because it is programmed in the DMA engine.

Is it possible to have debug session to check all LDC parameters?

Hi, Brijesh,

How to do this steps?

BRs

0 Brijesh Jadav 4 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

We can print the output address in the LDC node. We can put a print in the tivxVpacLdcProcess API in imaging\kernels\hwa\vpac_ldc\vx_vpac_ldc_target.c file, as shown below.

        for (out_cnt = 0u; out_cnt < ldc_obj->num_output; out_cnt ++)
        {
            frm = &ldc_obj->outFrm[out_cnt];
            for (plane_cnt = 0u; plane_cnt < TIVX_IMAGE_MAX_PLANES;
                plane_cnt ++)
            {
                frm->addr[plane_cnt] = tivxMemShared2PhysPtr(
                    out_frm_desc[out_cnt]->mem_ptr[plane_cnt].shared_ptr,
                    (int32_t)out_frm_desc[out_cnt]->mem_ptr[plane_cnt].mem_heap_region);
            }
            #if defined(VPAC3) || defined(VPAC3L)
            if(out_cnt == 0)
            {
                if(out_frm_desc[0] != NULL && out_frm_desc[1] != NULL && NULL != in_frm_desc[1])
                {
                    if((((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 ==out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format)))
                    {
                        frm->addr[0] = tivxMemShared2PhysPtr(
                                out_frm_desc[0]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[0]->mem_ptr[0].mem_heap_region);
                        frm->addr[1] = tivxMemShared2PhysPtr(
                                out_frm_desc[1]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[1]->mem_ptr[0].mem_heap_region);
                    }
                }
            }
            else
            {
                if(out_frm_desc[2] != NULL && out_frm_desc[3] != NULL && NULL != in_frm_desc[1])
                {
                    if((((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 ==out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format)))
                    {
                        frm->addr[0] = tivxMemShared2PhysPtr(
                                out_frm_desc[2]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[2]->mem_ptr[0].mem_heap_region);
                        frm->addr[1] = tivxMemShared2PhysPtr(
                                out_frm_desc[3]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[3]->mem_ptr[0].mem_heap_region);
                    }
                }
            }
            #endif
            VX_PRINT(VX_ZONE_ERROR, "LDC Output Address 0x%x 0x%x\n",
                frm->addr[0], frm->addr[1]);        
            outFrmList->numFrames ++;
        }

Regards,

Brijesh

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

The LDC output address print as below:

ldc_output_address.txt

0 Brijesh Jadav 4 months ago in reply to xie jc

TI__Guru**** 476235 points

Hi xie jc,

In the print log, i see that last output buffer address that LDC is getting is 0xbf082000 and this address is already used before, so most likely this is already accessible..

[MCU2_0] 157.326102 s: VX_ZONE_ERROR: [tivxVpacLdcProcess:543] LDC Output Address 0xbf082000 0x0

Are you using correct output image for the LDC? Because output address for chroma is 0x0.

Also are you using LDC output as graph parameters?

Regards,

Brijesh

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
Are you using correct output image for the LDC? Because output address for chroma is 0x0

How to know if the outimage is correct ？could you help to check the code we send you before?

Brijesh Jadav said:
Also are you using LDC output as graph parameters?

yes, because we need to share the LDC buffer

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
Are you using correct output image for the LDC? Because output address for chroma is 0x0.

where to control the chroma ?

0 Brijesh Jadav 4 months ago in reply to xie jc

TI__Guru**** 476235 points

hi Xie JC,

It depends on how you have created images. If you have created images of type NV12 in the application, then it would allocate the buffer for both the planes. So can you please check and confirm that you are using NV12 as output format for LDC?

Regards,

Brijesh

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Brijesh Jadav said:
So can you please check and confirm that you are using NV12 as output format for LDC?

Hi, Brijesh,

Yes, We are using NV12 as output format for LDC

0 Brijesh Jadav 4 months ago in reply to xie jc

TI__Guru**** 476235 points

Then is there an error in printing ie in below statement? Can you please use two different statements to print both the output addresses, ie for luma and for chroma?

VX_PRINT(VX_ZONE_ERROR, "LDC Output Address 0x%x 0x%x\n",
frm->addr[0], frm->addr[1]);

Regards,

Brijesh

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Brijesh Jadav said:
Then is there an error in printing ie in below statement?

No.

reproduce log:

ldc_block_reproduce.txt

vx_target_ldc.c

Fullscreen part_of_vx_target_ldc.c Download

static vx_status VX_CALLBACK tivxVpacLdcProcess(
       tivx_target_kernel_instance kernel,
       tivx_obj_desc_t *obj_desc[],
       uint16_t num_params, void *priv_arg)
{
    vx_status              status = (vx_status)VX_SUCCESS;
    int32_t                fvid2_status = FVID2_SOK;
    uint32_t               size;
    uint32_t               out_cnt;
    uint32_t               plane_cnt;
    Fvid2_Frame           *frm = NULL;
    tivx_obj_desc_image_t *in_frm_desc[2U] = {NULL};
    tivx_obj_desc_image_t *out_frm_desc[4U] = {NULL};
    tivxVpacLdcObj        *ldc_obj = NULL;
    Fvid2_FrameList       *inFrmList;
    Fvid2_FrameList       *outFrmList;
    uint64_t cur_time;

    if ( ((num_params != TIVX_KERNEL_VPAC_LDC_MAX_PARAMS)
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC_CONFIGURATION_IDX])
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC_IN0_IMG_IDX])
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC_OUT0_IMG_IDX]))
        && ((num_params != TIVX_KERNEL_VPAC_LDC2_MAX_PARAMS)
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC2_CONFIGURATION_IDX])
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC2_IN0_IMG_IDX])
        || (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT0_IMG_IDX])))
    {
        VX_PRINT(VX_ZONE_ERROR, "Invalid Descriptor\n");
        status = (vx_status)VX_FAILURE;
    }

    if ((vx_status)VX_SUCCESS == status)
    {
        status = (vx_status)VX_FAILURE;

        status = tivxGetTargetKernelInstanceContext(kernel,
            (void **)&ldc_obj, &size);

        if ((vx_status)VX_SUCCESS != status)
        {
            VX_PRINT(VX_ZONE_ERROR, "Failed to get Target Kernel\n");
        }
        else if ((NULL == ldc_obj) ||
            (sizeof(tivxVpacLdcObj) != size))
        {
            VX_PRINT(VX_ZONE_ERROR, "Invalid Ldc Object\n");
            status = (vx_status)VX_ERROR_INVALID_NODE;
        }
        else if ((1u == ldc_obj->ldc_cfg.enableOutput[1U]) &&
                (NULL == obj_desc[TIVX_KERNEL_VPAC_LDC_OUT1_IMG_IDX]))
        {
            VX_PRINT(VX_ZONE_ERROR, "Null Desc for output1\n");
            status = (vx_status)VX_FAILURE;
        }
        else
        {
            /* do nothing */
        }
    }

    if ((vx_status)VX_SUCCESS == status)
    {
        inFrmList = &ldc_obj->inFrmList;
        outFrmList = &ldc_obj->outFrmList;
        if(num_params == TIVX_KERNEL_VPAC_LDC_MAX_PARAMS)
        {
            in_frm_desc[0u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC_IN0_IMG_IDX];
            out_frm_desc[0u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC_OUT0_IMG_IDX];
            out_frm_desc[1u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC_OUT1_IMG_IDX];
        }
        if(num_params == TIVX_KERNEL_VPAC_LDC2_MAX_PARAMS)
        {
            in_frm_desc[0u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_IN0_IMG_IDX];
            in_frm_desc[1u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_IN1_IMG_IDX];
            out_frm_desc[0u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT0_IMG_IDX];
            out_frm_desc[1u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT1_IMG_IDX];
            out_frm_desc[2u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT2_IMG_IDX];
            out_frm_desc[3u] = (tivx_obj_desc_image_t *)
                obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT3_IMG_IDX];

            if(NULL != in_frm_desc[1])
            {
                out_frm_desc[1u] = (tivx_obj_desc_image_t *)
                    obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT2_IMG_IDX];
                out_frm_desc[2u] = (tivx_obj_desc_image_t *)
                    obj_desc[TIVX_KERNEL_VPAC_LDC2_OUT1_IMG_IDX];
            }
        }

        inFrmList->frames[0U] = &ldc_obj->inFrm;
        inFrmList->numFrames = 1U;
        outFrmList->frames[0U] = &ldc_obj->outFrm[0U];
        outFrmList->frames[1U] = &ldc_obj->outFrm[1U];
        outFrmList->numFrames = 0U;

        frm = &ldc_obj->inFrm;
        #if defined(VPAC3) || defined(VPAC3L)
		dddd
        if(in_frm_desc[0] != NULL && in_frm_desc[1] != NULL)
        {
            if((((vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[0]->format &&
                (vx_df_image)TIVX_DF_IMAGE_P12 == in_frm_desc[1]->format) ||
                ((vx_df_image)TIVX_DF_IMAGE_P12 == in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[1]->format) ||
                ((vx_df_image)TIVX_DF_IMAGE_P12 ==in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[1]->format) ||
                ((vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[0]->format &&
                (vx_df_image)TIVX_DF_IMAGE_P12 == in_frm_desc[1]->format) ||
                ((vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[1]->format) ||
                ((vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[1]->format) ||
                ((vx_df_image)TIVX_DF_IMAGE_P12 == in_frm_desc[0]->format &&
                (vx_df_image)TIVX_DF_IMAGE_P12 == in_frm_desc[1]->format) ||
                ((vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U8 == in_frm_desc[1]->format) ||
                ((vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[0]->format &&
                (vx_df_image)VX_DF_IMAGE_U16 == in_frm_desc[1]->format)))
            {
                frm->addr[0] = tivxMemShared2PhysPtr(
                        in_frm_desc[0]->mem_ptr[0].shared_ptr,
                        (int32_t)in_frm_desc[0]->mem_ptr[0].mem_heap_region);
                frm->addr[1] = tivxMemShared2PhysPtr(
                        in_frm_desc[1]->mem_ptr[0].shared_ptr,
                        (int32_t)in_frm_desc[1]->mem_ptr[0].mem_heap_region);
            }
        }
        else
        #endif
        {
            for (plane_cnt = 0u; plane_cnt < TIVX_IMAGE_MAX_PLANES; plane_cnt ++)
            {
                frm->addr[plane_cnt] = tivxMemShared2PhysPtr(
                in_frm_desc[0]->mem_ptr[plane_cnt].shared_ptr,
                (int32_t)in_frm_desc[0]->mem_ptr[plane_cnt].mem_heap_region);
				VX_PRINT(VX_ZONE_ERROR, "111111plance_cnt: %d, 0x%lx\n", plane_cnt, frm->addr[plane_cnt]);
            }
        }

		VX_PRINT(VX_ZONE_ERROR, "111111LDC Output Address 0x%x 0x%x, 0x%x, 0x%x\n", frm->addr[0], frm->addr[1], frm->addr[2], frm->addr[3]);
        for (out_cnt = 0u; out_cnt < ldc_obj->num_output; out_cnt ++)
        {
            frm = &ldc_obj->outFrm[out_cnt];
            for (plane_cnt = 0u; plane_cnt < TIVX_IMAGE_MAX_PLANES;
                plane_cnt ++)
            {
                frm->addr[plane_cnt] = tivxMemShared2PhysPtr(
                    out_frm_desc[out_cnt]->mem_ptr[plane_cnt].shared_ptr,
                    (int32_t)out_frm_desc[out_cnt]->mem_ptr[plane_cnt].mem_heap_region);
				VX_PRINT(VX_ZONE_ERROR, "22222plance_cnt: %d, 0x%lx\n", plane_cnt, frm->addr[plane_cnt]);
            }
            #if defined(VPAC3) || defined(VPAC3L)
			dddd
            if(out_cnt == 0)
            {
                if(out_frm_desc[0] != NULL && out_frm_desc[1] != NULL && NULL != in_frm_desc[1])
                {
                    if((((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 ==out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[0]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[1]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[0]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[1]->format)))
                    {
                        frm->addr[0] = tivxMemShared2PhysPtr(
                                out_frm_desc[0]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[0]->mem_ptr[0].mem_heap_region);
                        frm->addr[1] = tivxMemShared2PhysPtr(
                                out_frm_desc[1]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[1]->mem_ptr[0].mem_heap_region);
                    }
                }
            }
            else
            {
                if(out_frm_desc[2] != NULL && out_frm_desc[3] != NULL && NULL != in_frm_desc[1])
                {
                    if((((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 ==out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format) ||
                        ((vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[2]->format &&
                        (vx_df_image)TIVX_DF_IMAGE_P12 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U8 == out_frm_desc[3]->format) ||
                        ((vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[2]->format &&
                        (vx_df_image)VX_DF_IMAGE_U16 == out_frm_desc[3]->format)))
                    {
                        frm->addr[0] = tivxMemShared2PhysPtr(
                                out_frm_desc[2]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[2]->mem_ptr[0].mem_heap_region);
                        frm->addr[1] = tivxMemShared2PhysPtr(
                                out_frm_desc[3]->mem_ptr[0].shared_ptr,
                                (int32_t)out_frm_desc[3]->mem_ptr[0].mem_heap_region);
                    }
                }
            }
            #endif

            VX_PRINT(VX_ZONE_ERROR, "22222LDC Output Address 0x%x 0x%x, 0x%x, 0x%x\n", frm->addr[0], frm->addr[1], frm->addr[2], frm->addr[3]);

            outFrmList->numFrames ++;
        }

0 xie jc 4 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi, Brijesh,

Any ideas where the problem might be? Are we using it incorrectly?

BRs

Processors

Processors forum

TDA4VM-Q1: capture block at dequeue