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OMAP 3530 HS, VS timings

Other Parts Discussed in Thread: OMAP3530

 Background:  

We are currently working on a product development which involves raw image capture on OMAP3530 and the hardware used is a Gumstix board.

We were receiving the interrupts however while processing the interrupt we observe the issue of “CCDC busy” and the image capture of 512x512 was not getting captured.

1.       We have captured 12bit data raw data and directly written the same to the memory.

2.       Pixel clock is 9.56Mhz, Hsync is 37.3Khz and Vsync is 72Hz. All these are input to OMAP3530.

This issue was because of the HS, VS and pixel clock timings and we modified the Hsyc, Vsync and pixel clock on our test board and we have captured the images upto 512x512 resolution.

 

We are facing one more issue as mentioned below:

We have the test board working with 512x512, but we have final camera unit board that we want to test for same resolution seems to fail to capture 512x512 images.

Though the same clocks settings with the actual camera unit are done, still we are not getting images captured successfully. Only difference that we observe between these boards is that the Hsync and Vsync rising edge doesn’t coincide.

 

So wanted to confirm the following assumptions

1.       The first positive edge of the clock following a positive edge of either Vsync or Hsync should trigger the new active frame or line.

2.       Both Vsync and Hsync positive edges should coincide.

 

Can you please confirm that these assumptions are must require conditions for OMAP3530??

 

Additional details related to timings on Camera unit board

Vsync: 55.5 Hz, Total=18.0 ms, Active=17.9 ms, Inactive=125 us

Hsync: 28.4 kHz, Total=35.2 us, Active=34.9 us, Inactive=0.27 us

Pixel Clock: 14.54 MHz, Total=69 ns

 

Regards,

Shriharsh

Maven Systems Pvt. Ltd.

+91-9922991230

  • Additional information for the image capture of full resolution issue that we are observing,

     

    Hardware signals that are input to the OMAP3530

    Vsync: 10.28 Hz, Total= 97.2 ms, Active(High)= 95.6 ms, Inactive(Low)= 1.6 ms
    Hsync: 5.26 kHz, Total=190 us, Active= 187 us, Inactive= 2.8 us
    Pixel Clock: 2.68 MHz, Total= 372 ns

    So active resolution is our case is 503x503.  Total Pixels = 512x512

    With these hardware signals we are able to capture image only upto the resolution of 503x490.

    When we reduce the pixel clock to 1Mhz and the harware signals are as below,

    Vsync: 3.8 Hz, Total= 263 ms, Active= 257.7 ms, Inactive= 5.3 ms
    Hsync: 1.9 kHz, Total=526 us, Active= 515.5 us, Inactive= 10.5 us
    Pixel Clock: 1 MHz, Total= 100 ns

    So active resolution is our case is 503x503.  Total Pixels = 512x512

    With these hardware settings we are able to capture the images only upto the resolution of 503x497.

     

    Can you help me understand why does reduction in pixel clock from 2.6Mhz to 1Mhz help me capture 7 lines more in the later settings from the prev one?? Though we are not able to capture full resolution image of 503x503 in either condition.

     

    NOTE: HS and VS signals are generated from the pixel clock with the calculation as HS = Pclk/512 and VS = HS/512.

    Regards,

    Shriharsh Datar

    Maven Systems Pvt Ltd

    +91-9922991230

  • Shriharsh,

    Have you connected a logic analyzer to validate timings of the HS/VS signals? The timings for pclk of 2.68 looks right (HS=510.75, VS=502.69). However, for pclk 1Mz HS=5260 and VS=5155. Are these the tru values observed by you? Please share your CCDC/ISP register configuration also, making sure that CCDC_VERT_LINES and CCDC_HSIZE_OFF is programmed correctly for the expected values is important.

    Thank you.

    Regards, Punya

  • In both the cases. i.e.  when the pixel clock was 2.6Mhz and 1Mhz the total resolution was 512x512.

    As the divider circuitry is same in both the cases. So actual capture should have been 503x503 in both the cases. Only diff that we observe is the actual image getting captured for 2.6Mhz is 503x490 and that for 1Mhz is 503x497.

    We have observed the signals on the oscilloscope and with the USB logic analyzer.

    Register dump for CCDC and ISP registers for 512x500 capture

    ISPCCDC: ###CCDC PCR=0x0
    ISPCCDC: ISP_CTRL =0x29c100
    ISPCCDC: ###ISP_CTRL in ccdc =0x29c100
    ISPCCDC: ###ISP_IRQ0ENABLE in ccdc =0x0
    ISPCCDC: ###ISP_IRQ0STATUS in ccdc =0x80000300
    ISPCCDC: ###CCDC SYN_MODE=0x30400
    ISPCCDC: ###CCDC HORZ_INFO=0x1ff
    ISPCCDC: ###CCDC VERT_START=0x0
    ISPCCDC: ###CCDC VERT_LINES=0x1f2
    ISPCCDC: ###CCDC CULLING=0xffff00ff
    ISPCCDC: ###CCDC HSIZE_OFF=0x400
    ISPCCDC: ###CCDC SDOFST=0x0
    ISPCCDC: ###CCDC SDR_ADDR=0x0
    ISPCCDC: ###CCDC CLAMP=0x10
    ISPCCDC: ###CCDC COLPTN=0x0
    ISPCCDC: ###CCDC VDINT=0x1f10064
    ISPCCDC: ###CCDC CFG=0x8000
    ISPCCDC: ###CCDC VP_OUT=0x0
    ISPCCDC: ###CCDC_SDR_ADDR= 0x0
    ISPCCDC: ###CCDC FMTCFG=0x0
    ISPCCDC: ###CCDC FMT_HORZ=0x1f4
    ISPCCDC: ###CCDC FMT_VERT=0x1f4
    ISPCCDC: ###CCDC LSC_CONFIG=0x6608
    ISPCCDC: ###CCDC LSC_INIT=0x0
    ISPCCDC: ###CCDC LSC_TABLE BASE=0x1000
    ISPCCDC: ###CCDC LSC TABLE OFFSET=0x60

    Regards,

    Shriharsh Datar

    Maven Systems Pvt Ltd

    +91-9922991230

  • Inputs from Punya...

    Looking at the register configuration posted on the e2e forum looks like the intention is to configure CCDC for 8-bit, 16bpp RAW capture, is this correct? Assuming so, there are a few register configuration discrepancies that I observe (listed below). The missing pixels could be due to the fact that ISP and CCDC are configured to expect a different image resolution while the data being input to the ISP is different. 

    1. The pack8 and datasize configurations do not match
      1. SYN_MODE.PACK8 is set to 0x0 which enables 16bpp
      2. SYN_MODE.DATSIZ is set to 0x4 which is 12-bit data capture. This should be 0x0 and ISP_CTRL.PAR_BRIDGE should be configured for 16bpp capture
      3. CCDC_HORZ_INFO, CCDC_VERT_START, and CCDC_VERT_LINES are the primary registers that have to be configured correctly for correct data capture. Here,
        1. CCDC_HORZ_INFO=511, correct for 512 capture
        2. CCDC_VERT_START=0, correct
        3. CCDC_VERT_LINES=498, should be 1FF for 512 capture
        4. HSIZE_OFF is currently set to 0x400, this is correct for 16bpp capture
        5. CCDC_FMT_HORZ and CCDC_FMT_VERT should be set to 0x200 for 512x512 capture, currently 500.