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J784S4XEVM: Error routing events/interrupts from MAIN Domain

Mathuran Kandeepan
Prodigy 30 points
Part Number: J784S4XEVM

Tool/software:

Hello,

I am working on the J784S4XEVM board and currently focusing on the Interrupt Aggregator (INTA) and Interrupt Router (INTRTR) drivers.

I am facing an issue where I can successfully route an interrupt from the GPIOMUX_INTRTR0 instance when I configured it from the MCU domain, but not when it is configured from the MAIN domain.

Similarly, I encounter the same issue when handling a global event from NAVSS0_UDMASS_INTA_0. I manage to map a event by configuring the GLOBAL_EVENT_SEVT table from the MCU domain, but not from the MAIN domain. What could be causing this?

I have already checked the Resource Manager, and everything seems correct.

I suspect that other components might also be affected by this issue. What steps should I take to resolve this?

Any insights or guidance would be greatly appreciated.

Thanks!



  • 0
    TI__Mastermind 19460 points

    Hi,

    Can you confirm you are using RTOS and what SDK version?

    Mathuran Kandeepan said:
    I am facing an issue where I can successfully route an interrupt from the GPIOMUX_INTRTR0 instance when I configured it from the MCU domain, but not when it is configured from the MAIN domain.

    Can you clarify if you mean you are having issues when running your application on Main domain R5F or routing main domain GPIO? 

    Have you ran the GPIO Led blink example and stepped through the code? This example within the PDK shows how to set up and route interrupts for both WKUP and Main domain GPIO on both MCU and Main R5F cores.

    Mathuran Kandeepan said:
    Similarly, I encounter the same issue when handling a global event from NAVSS0_UDMASS_INTA_0. I manage to map a event by configuring the GLOBAL_EVENT_SEVT table from the MCU domain, but not from the MAIN domain. What could be causing this?

    I will loop in an expert to help with this separately.

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Prodigy 30 points

    Hello,

    Neehar Sawant said:
    Can you confirm you are using RTOS and what SDK version?

    Negative, I am running my baremetal application.

    Neehar Sawant said:
    Have you ran the GPIO Led blink example and stepped through the code? This example within the PDK shows how to set up and route interrupts for both WKUP and Main domain GPIO on both MCU and Main R5F cores.

    I'm having trouble when i'm configuring the GPIOMUX_INTRTR0. I have no issue configuring this interrupt router from the R5F MCU core. However, configuring this interrupt router from a R5F MAIN core seems problematic. I tested on all instances of the interrupt routers and noticed the same issue on the following instances: WKUP_GPIOMUX_INTRTR0,  MAIN2MCU_LVL_INTRTR0 and MAIN2MCU_PLS_INTRTR0.

    Neehar Sawant said:
    Can you clarify if you mean you are having issues when running your application on Main domain R5F or routing main domain GPIO? 

    Thanks for this example! I looked to the GPIO_Baremetal_LedBlink_TestApp application executed from the R5F MAIN core and I noticed that the interrupt configuration is done by the sciserver, so I assume by the R5F MCU core. Is there any other way to do it directly from the  R5F MAIN core?

    Thanks,

    Mathuran

  • 0 in reply to Mathuran Kandeepan
    TI__Mastermind 19460 points

    Hi Mathuran,

    Let me look into this further and get back to you. 

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    TI__Mastermind 19460 points

    Hi Mathuran,

    Mathuran Kandeepan said:
    However, configuring this interrupt router from a R5F MAIN core seems problematic. I tested on all instances of the interrupt routers and noticed the same issue on the following instances: WKUP_GPIOMUX_INTRTR0,  MAIN2MCU_LVL_INTRTR0 and MAIN2MCU_PLS_INTRTR0.

    If you are running this application on the R5F Main core and setting up an interrupt for main GPIO, you will only be required to use the GPIOMUX_INTRTR0 interrupt router. You will not need MAIN2MCU unless you trying to interrupt an MCU core for main GPIO.

    Mathuran Kandeepan said:
    Is there any other way to do it directly from the  R5F MAIN core?

    Please take a look at the following documentation. We perform all our interrupt registration using sciclient requests to sciserver that is running on MCU1_0. This is our standard approach in all of our examples. We do not support a way to do interrupt registration directly from Main R5 core as SYSFW is required to be ran on MCU1_0.

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Prodigy 30 points

    Hi Neehar,

    Thanks a lot for this information. It is pretty clear!


    Mathuran Kandeepan said:
    Similarly, I encounter the same issue when handling a global event from NAVSS0_UDMASS_INTA_0. I manage to map a event by configuring the GLOBAL_EVENT_SEVT table from the MCU domain, but not from the MAIN domain. What could be causing this?


    Have you got more details regarding this issue?

    Thanks,

    Mathuran

  • 0 in reply to Mathuran Kandeepan
    TI__Mastermind 19460 points

    Hi Mathuran,

    Yes, sorry for the delay. I will have an expert respond to this.

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    TI__Mastermind 19460 points

    Hi Mathuran,

    Mathuran Kandeepan said:

    I have already checked the Resource Manager, and everything seems correct.

    Have you made any changes to the default rm board cfg?

    Which main domain core are you have issues with?

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Prodigy 30 points

    Hi,

    Sorry fort the delay.

    I'm using the default rm board config.

    I have this issue with all main domain core.

    Thanks

  • 0 in reply to Mathuran Kandeepan
    TI__Mastermind 19460 points

    Hi Mathuran,

    Have you checked the response from Sciclient_rmGetResourceRange() API to confirm the resources are allocated for Main domain?

    Additionally, can you provide the configuration and code you use to set up event for NAVSS0_UDMASS_INTA_0 for MCU and Main domain?

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    TI__Mastermind 19460 points

    Hi Mathuran,

    Following up, is this issue still open?

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Prodigy 30 points

    Hi,

    I modified the default Resource Manager configuration sent to the TIFS by allocating all resources to all hosts. So, every host should now have access to all resources.

    Unfortunately, I cannot provide you the source code.

    However, could you test or share a simple example where you successfully configured the GLOBAL_EVENT_SEVT table of the NAVSS0_UDMASS_INTA_0 instance from an A72 core?

    Thanks,

    Mathuran

  • 0 in reply to Mathuran Kandeepan
    TI__Mastermind 19460 points

    Hi Mathuran,

    Let me look try and see if we have an example and I will get back to you.

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Prodigy 30 points

    Hi Neehar,

    Any news?

    Thanks,

    Mathuran

  • 0 in reply to Mathuran Kandeepan
    TI__Mastermind 19460 points

    Hi Mathuran,

    Have you checked the response from Sciclient_rmGetResourceRange() API to fully confirm the resources are allocated for Main domain?

    Thanks,

    Neehar