C5515 boots from SPI Flash but gets stuck on EMIF access

Hi again,

We have fixed one error in the setup script, but see that the RBL and Timer0 prevents booting from mSDRAM, since the EMIF setup must get a Reset that also affect Timer0.
Please read our questions in red below, and advice how to overcome the EMIF setup issue:

"I have made  a mistake in the previous scripts I send over last week. There is two missing comment parenthesis. 
I.e. two registries wasn't loaded by the HEX55. A fix of this mistake doesn't solve the main problem, but we got a more stable debug connection for investigation the stucked system after booting from flash. Together with a colleague with long TI experience, we have made a deeper investigation.

A simple test program was created. It just toggles the XF pin.
We have linked it in two version
LED_INT runs in internal RAM only
LED_EXT runs in external mSDRAM

Both of them runs as expected in debug mode with emulator.

Boot from flash without init EMIF by register setting.
LED_INT boots and runs the main();
LED_EXT crash when main() is called. Reason is that no code is loaded to EXT RAM by RBL.

Boot from flash with init of EMIF by register setting according to EMIF manual for uSDRAM.
LED_INT boots but don't execute the main();
LED_EXT boots but don't execute the main(); We can force code execution by issue a run to main command from the debugger.
Reason why main() is not running:
The boot loader is stuck because it waits for the timeout of Timer0.
Timer0 is stopped by the peripheral reset of EMIF. Both Timers and EMIF uses the same reset bit in the PRCR register.
See SPRUFX5A 1.7.5.2

 Boot from flash with init EMIF by register setting, but without peripheral reset of EMIF.
LED_INT boots and execute the main();
LED_EXT boots but don't execute the main()

 Boot from flash with init EMIF by register setting, with peripheral reset of EMIF and restart of timer0.
LED_INT boots and execute the main();
LED_EXT boots but crash when execute the main()

-In this case a known bug in RBL cause the problem?
Just before the RBL releases control to the user code, all peripheral clocks will be "off". Thus the EMIF lost the clock and the mSDRAM lost refresh.

Conclusion

The RBL is not useable for booloading code into External uSDRAM !?!
 The description in SPRS645D section 4.4 Boot Sequence is not reliable. It claims that Timer0 starts after register settings.
 

Question:

-What configurations have to be done to get a work around the limitation in the RBL?
-Is it possible to use the RBL to boot to Ext mSDRAM or it is nessecery to write a second bootloader?

I think only a person with access to the source of the RBL can give a correct answer.
The default SPI clock is 500kHz. We want to speed up the SPI Flash boot process much as possible. -How to do this?
There is a warning to change the PLL by registry setting in the BSL. -What will happen if we do??

Command file for HEX55.EXE

-v5505
-serial8
-map hex55sdram.map
-boot
-o out.bin
-b                        /* -b, Binary format */
                         
                               /* setup PLL */

-reg_config 0x1c02,0x0000 /* Activate all perifial clock...         */
-reg_config 0x1c03,0x0000 /* ....IMIF clock is needed               */

-reg_config 0x1c1f,0x0000 /* bypass PLL                             */
-reg_config 0x1c20,0x8be8 /* 0x8be8 - 98MHz, Set PLL to 98MHZ PLLCTL0   */
-reg_config 0x1c21,0x8000 /* PLL CTL1                                      */
-reg_config 0x1c22,0x0806 /* PLL CTL2                                      */
-reg_config 0x1c23,0x0000 /* PLL CTL3                                      */
-delay 0x7fff             /* wait 0x7fff                                   */
-reg_config 0x1c1f,0x0001 /* remove bypass                                 */

                          /* setup SPI divider */
/*-reg_config 0x3000,0x0019  set SPI divider to 25 -> 4MHz                */
/*-reg_config 0x3a04,0x0101   set SD_FLASH clock divisor to 1 -> 25MHz    */
                         
                               /* setup mSDRAM for MT48H4M16LF-8 */
-reg_config 0x1c05,0x0002 /* reset EMIF , will also reset TIMERS?          */
-delay 0x7fff             /* wait 0xff                                     */
-reg_config 0x1c26,0x0000 /* EDIV active Sysclock divided by 2 fir SDRAM   */
-reg_config 0x1c1e,0x0001 /* enable SDRAM clock                            */
-reg_config 0x1c33,0x0000 /*                                               */
-reg_config 0x1020,0x4710 /*  SDTMR1 for timing details see "SPRUGU6.PDF"  */
-reg_config 0x1021,0x3911 /*  SDTMR2                                       */
-reg_config 0x103c,0x0007 /*  SDSRETR                                      */
-reg_config 0x100c,0x04e3 /*  SDRCR                                        */
-reg_config 0x1008,0x4720 /*  SDCR1                                        */
-reg_config 0x1009,0x0001 /*  SDCR2    0x8001 = selfrefresh                */
                               /*           0x0001 = refresh by EMIF            */
-reg_config 0x100c,0x061a /*                                               */                  

-reg_config 0x1812,0xc000 /* Restart of timer0*/
-reg_config 0x1813,0x0012
-reg_config 0x1811,0x0000
-reg_config 0x1810,0x8001

 
Source of information

SPRUGU6 EMIF user's guide
SPRABD7 bootloader appnote
SPRS645D data sheet TMS320C5515

4.4 Boot Sequence
9. Test for 16-bit and 24-bit SPI EEPROM boot on SPI_CS[0] with 500-KHz clock rate and for Parallel
Port Mode on External bus Selection Register set to 5, then set to 6:
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode.
(c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 10.
(d) Set Register Configuration, if present in boot image.
(e) Attempt SPI Serial Memory boot, go to step 15.

15. Enable TIMER0 to start counting 200 ms.
16. Ensure a minimum of 200 ms has elapsed since step 15 before proceeding to execute the boot loaded
code.
17. Jump to the entry point specified in the boot image.

4.4.2 Boot Configuration
After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the
system clock to 12.288 MHz (multiply the 32.768-KHz RTC oscillator clock by 375). If CLK_SEL = 1, the
Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN
pin.
Note:
• When CLK_SEL =1, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz.
• The on-chip Bootloader allows for DSP registers to be configured during the boot process. However,
this feature must not be used to change the output frequency of the system clock generator during the
boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The
bootloader register modification feature must not modify the Timer0 registers.
After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the
bootloader queries each peripheral to determine if it can boot from that peripheral. At that time, the
individual peripheral clocks will be enabled for the query and then disabled when the bootloader is finished
with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will
be "off" and all domains in the ICR, except the CPU domain, will be idled.
4.4.3 DSP

Table 3-19. Regulators and Power Management Terminal Functions (continued
BG_CAP B13 A, I/O This external capacitor provides filtering for stable reference voltages & currents
generated by the bandgap circuit. The bandgap produces the references for use by
the System PLL, SAR, and POR circuits.

SPRUFX5A - 1.7.5.2
Peripheral Reset Control Register (PRCR) [1C05h]

/Magnus and David