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AM625: RAT Related Questions

Mari Tsunoda
Expert 5726 points
Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi Team,

Is it possible to configure the RAT in sysconfig for a specific GPIO bank? They specifically want to configure for the pins marked as over ride as listed below in the table.

Best regards,

Mari Tsunoda

  • 0
    TI__Mastermind 49808 points

    Hi Mari,

    Mari Tsunoda said:

    They specifically want to configure for the pins marked as over ride as listed below in the table.

    From the table, I can see that customer want to configure RAT for GPIO Bank 2, Bank 4 and 2 pins of Bank 5 as well.

    May I know what is the reason to do RAT translation for those specific reasons?

    From which core they are running the application? What is the version of MCU+SDK used?

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    TI__Expert 5726 points

    Hi Tushar,

    Thanks for the response.

    They want to control these pins from M4F core. It says in the TRM that they will need to map these addresses via RAT. Is this right?

    Let me check about MCU+SDK version

    Best regards,

    Mari Tsunoda

  • 0 in reply to Mari Tsunoda
    TI__Mastermind 49808 points

    Hi Mari,

    The base address for GPIO0, GPIO1 and MCU_GPIO are 0x600000, 0x601000 and 0x4201000 respectively. 

    Please refer below image.

    The above mentioned region are already configured to have RAT translation. Customer doesn't need to worry the RAT configuration for this.

    Please refer below image.

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    TI__Expert 5726 points

    Hi Tushar,

    Thanks again for the quick response.

    So let me check my understanding. If A53 core is using the GPIO_0_48~GPIO_0_63, then the configuration shown in the sysconfig screenshot below wouldn't work because it is also establishing the aforementioned pins as M4F control right?

    In other words, since the RAT configuration includes ALL banks in GPIO0 for M4F core, A53 cores would not be able to control Bank 1&3. 

    In that case, what should the configuration look like?

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Mastermind 49808 points

    Hi Mari,

    Mari Tsunoda said:
    If A53 core is using the GPIO_0_48~GPIO_0_63, then the configuration shown in the sysconfig screenshot below wouldn't work because it is also establishing the aforementioned pins as M4F control right?

    Yes the above RAT configuration are done for M4F core and A53 will have no effect of it. A53 doesn't require any RAT configuration as it can access the complete 36bit addressable SOC memory range.

    Mari Tsunoda said:
    In other words, since the RAT configuration includes ALL banks in GPIO0 for M4F core, A53 cores would not be able to control Bank 1&3.

    RAT configuration doesn't set any firewall or restriction for other cores access. You should be able to access it via A53 also(in RTOS/noRTOS). 

    Regards,

    Tushar