Hello,
My question about ISR latency of TI under WinCE.
I can't found ability to make stable ISR starting time on EVM board with DM3730 module. And I still looked for it.
We are using Adeneo latest Windows CE 6.0 BSP for OMAP/AM35xx/DM37xx processor modules (version BSP_WINCE_ARM_A8_01_02_00_Source)
We found already that the extended TI PM have affected to ISR and make unpredictable ISR start delays. Therefore, additional CPU specific PM "PMExt" disabled completely in WinCE OS design. Just "Power management Full" enabled on "Core OS services".
Also, There is minimal other interrupt sources which can affect to ISR processing. And we control it for minimal activity.
ISR time measurement made by oscilloscope and ISR time vary from 5 to 700 us.
The only way to correct ISR behaivior is manuall replacement of g_wakeupLatencyConstraintTickCount to [1-5] value instead MAX_INT.
It make ISR average time better, but not help make stable maximum time. It isn't solution.
Our goal is stable ISR latency <100us all time OS runnning. Any advices how to make it?
UPDATE: I'm newbie with TI specific power management, don't make attention