In section 2.5.6.8 of the , it states:
"the EMIFA does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. One way to work around this limitation is to use a GPIO pin to drive the CE signal of the NAND Flash device."
Can I use any GPIO pin, even one that is multiplexed, but unused, with the EMIFA interface?
Thanks.
Luc
