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Cache_inv scope problem

gaotai zhang
Intellectual 415 points


 Hi,

     The SYS/BIOS provides Cache module and API for users . I'm concerned about the usage of Cache_inv function. If I first use Cache_inv to invalidate a range of memory address ,then read data from the address range, the data will be read from memory instead of cache,of course .If I do a second read from the same address accessed in the first read, will I be reading from cache or memory? In other words , what is the functioning scope of a Cache_inv,  One read or multiple reads?

Thanks,

Roy

  • 0
    TI__Genius 17205 points

    gaotai zhang said:
    If I first use Cache_inv to invalidate a range of memory address ,then read data from the address range, the data will be read from memory instead of cache,of course .If I do a second read from the same address accessed in the first read, will I be reading from cache or memory?

    You can't/shouldn't know, at least in a multi-threaded system.  At any point in time, the cache lines you _just_ read may be needed by a higher priority task/SWI/HWI in your system, which may result in the content of those cache lines being evicted.  If that happens, your next read of that memory address will [again] go out to external memory.

    However, if those cache lines _weren't_ evicted, your next read will be able to fetch that memory from the cache and avoid the external memory fetch.  Regardless, your code shouldn't be written to know these details.

    There are some interesting cache-related articles here:

    http://processors.wiki.ti.com/index.php/Cache_Management

    Chris