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DRA821U: Problem Reading UDMA from device connected as PCIE endpoint

Luke
Expert 4405 points

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Tool/software:

Hi team,

My customer has the following problem with reading via a UDMA from a device connected as a PCIE endpoint:

  • They have a custom board based on DRA821 chip with VxWorks 24.03
  • When they use a UDMA channel configured to 64-byte transfers, they receive the correct data from the endpoint.
  • When they try to use the UDMA channel configured to 128 or 256-byte transfers:
    • They get only the first 64-byte block of the data and then the UDMA enters into the error state
    • All subsequent calls to the UDMA channel fail with error
    • On the endpoint side they see that it gets two 64-byte requests. The 2nd one is received before the data for the 1st one is sent
  • They have already tried:
    • To change configuration of a MRRS and a MPS fields of a MRPCIE_CORE_PFn_I_PCIE_DEV_CTRL_STATUS register
    • To change configuration of a burst size in UDMA_TCFG and UDMA_RCFG registers

Can you advise please what are we missing or doing wrong?

Best,

Luke

  • +1
    TI__Guru 59803 points

    Hi Luke,

    I would recommend customer to contact WindRiver as well to see if this is a known issue for them, since VxWorks is not an OS that TI directly supports. 

    If it is general questions about registers or our Linux driver that is part of TI PSDK Linux, then here we can provide better support. 

    In any case, for 128 byte or more, I have read in our TRM about some limitations. Specifically, below excerpt about "The PCIe subsystem imposes a limitation of a maximum of 128-byte outbound read/write command." and how this can be smaller if not aligned to an 8 byte boundary:

    I have not seen a case where this has been an issue for the Linux driver that TI provides, but maybe this limitation is causing issues?

    Regards,

    Takuma