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DM8148 GPMC Series Resistors

Michael Hallak-Stamler
Prodigy 205 points

The Mistral EVM has series resistors on all GPMC lines including address and data. Is this really necessary?? Isn't it enough to for clock only?

 

  • 0
    TI__Intellectual 1040 points

    Michael,

    GPMC may not run as fast as say, DDR2 or DDR3 but, our main concern here is the fast edge rates of the signals.  Depending on your design and board stack-up, you may not need them.  But, I prefer the ability to tweak the circuit if need be to reduce the ringing effects of impedance mismatch from the buffer to the board.  Plus they are so cheap, they are practically free! :)

    Best regards,
    Scott

  • 0 in reply to ScottB
    Prodigy 205 points

     But why only on the data lines and not the address lines??

  • 0 in reply to ScottB
    Prodigy 205 points

    Hi Scott,

    Except for very fast  busses, such as DDR, generally bus signals are only terminated for clocks as far as signal integrity is concerned. Other reasons to use series termination is to control ringing for EMC reasons. 

    The GPMC bus is no more than 100 Mhz so I don't see why there should be data series resistors. In many designs, such as ours, there are serious space limitations.

    Has TI performed simulations to determine if these resistors on the data and address lines are really necessary for signal integrity?

    Thanks

    Michael

  • 0 in reply to Michael Hallak-Stamler
    TI__Intellectual 1040 points

    Michael,

    The EVMs are designed before we get silicon.  At this very early stage we design with flexibility and options to tweak circuits, if needed.  I do not know of a study where the termination resistors where 0 ohmed out to check functionality.

    There is no requirement saying termination resistors are needed for the GPMC bus.

    Best regards,
    Scott

  • 0 in reply to ScottB
    Prodigy 160 points

    Gentlement,

    GPMC bus question.

    In the DM8148 datasheet and pinmux tool, one can find 8x Chip Select on the GPMC (CS[0] to CS[7]), and we have peripherals attached to CS[7] (pin R24).

    In the TRM (SPRUGZ8A), pages 1540, one can read that the GPMC memory space is divided into 6 (not 8 !) chip-selects. And page 1541, note 1, "i" is from 0 to 5.

    I suppose that those are errors, and we should read "8 chip selects", with "i" going from 0  to 7 (which perfectly fills the GPMC registers address space table 11-55) ?

    Please advise.  Regards,

  • 0 in reply to Jean-Michel CAPITAN
    TI__Guru**** 170625 points

    hi Jean-Michel,

    Yes, GPMC is divided into 8: GPMC_CS[7:0]. The DataSheet is the correct one.

    Best regards,

    Pavel