TDA4VM: Multi UDMA configure for each MCSPI channel

Jiang Liu

Part Number: TDA4VM
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

We have new design request TWO MCSPI ports, how to configure UDMA for each MCSPI port, I know how to configure a UDMA to one MCSPI port. below is my code for configure one MCSPI port, the Udma_init() seems can be called once, but how do I create one more UDMA for second SPI?

Udma_DrvHandle MCSPIApp_udmaInit(SPI_v1_HWAttrs *cfg)
{
int32_t retVal = UDMA_SOK;
Udma_InitPrms initPrms;
uint32_t instId;

if (gDrvHandle == NULL) /* PRQA S 2991, 2994 */
{
/* UDMA driver init */
#if defined (SOC_AM64X)
/* Use Block Copy DMA instance for AM64x */
instId = UDMA_INST_ID_BCDMA_0;
#else
/* Use MCU NAVSS for MCU domain cores. Rest cores all uses Main NAVSS */
#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
instId = UDMA_INST_ID_MCU_0;
#else
instId = UDMA_INST_ID_MAIN_0;
#endif
#endif
(void)UdmaInitPrms_init(instId, &initPrms);
retVal = Udma_init(&gUdmaDrvObj, &initPrms);
if(UDMA_SOK == retVal)
{
gDrvHandle = &gUdmaDrvObj;
}
}

if(gDrvHandle != NULL)
{
gDrvHandle = &gUdmaDrvObj;

gUdmaInfo.txChHandle = (void *)&gUdmaTxChObj;
gUdmaInfo.rxChHandle = (void *)&gUdmaRxChObj;
gUdmaInfo.txRingMem = (void *)&gTxRingMem[0];
gUdmaInfo.cqTxRingMem = (void *)&gTxCompRingMem[0];
gUdmaInfo.rxRingMem = (void *)&gRxRingMem[0];
gUdmaInfo.cqRxRingMem = (void *)&gRxCompRingMem[0];
gUdmaInfo.txHpdMem = (void *)&gUdmaTxHpdMem[0];
gUdmaInfo.rxHpdMem = (void *)&gUdmaRxHpdMem[0];
gUdmaInfo.txEventHandle = (void *)&gUdmaTxCqEventObj;
gUdmaInfo.rxEventHandle = (void *)&gUdmaRxCqEventObj;
cfg->dmaInfo = &gUdmaInfo;
}
else
{
/* UART_printf("MCSPIApp_udmaInit: Udma_init failed with error code: %d\n", retVal); */
}

return (gDrvHandle);
}

SPI_HWAttrs spi_cfg =
{
.baseAddr = CSL_MCSPI0_CFG_BASE,
.intNum = CSLR_MAIN2MCU_LVL_INTRTR0_IN_MCSPI0_INTR_SPI_0,
.pinMode = (uint32_t)SPI_PINMODE_4_PIN,
.chNum = MCSPI_CHANNEL_0,
// .chMode = MCSPI_SINGLE_CH,
.chMode = MCSPI_MULTI_CH,
.enableIntr = (bool)ME_FALSE,
.inputClkFreq = 48000000U,
.initDelay = MCSPI_INITDLY_0,
.rxTrigLvl = MCSPI_RX_TX_FIFO_SIZE,
.txTrigLvl = MCSPI_RX_TX_FIFO_SIZE,
.chnCfg =
{
[0] =
{
.csPolarity = MCSPI_CS_POL_LOW,
.dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_7,
.tcs = MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
.trMode = MCSPI_TX_RX_MODE,
},
[1] =
{
.csPolarity = MCSPI_CS_POL_LOW,
.dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_7,
.tcs = MCSPI_CH1CONF_TCS1_ZEROCYCLEDLY,
.trMode = MCSPI_TX_RX_MODE,
},
},
.rxDmaEventNumber = CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX,
.txDmaEventNumber = CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX,

};

spi_cfg.edmaHandle = (void *)MCSPIApp_udmaInit(&spi_cfg);
spi_cfg.dmaMode = (bool)TRUE;

5 months ago

0 Tarun Mukesh Puvvada 5 months ago

TI__Mastermind 48486 points

Hello,

I think you are talking here about PDK driver ?

Have you see MCAL driver for SPI with DMA for all multi channel configuration on how this is done.

static const Spi_DmaEventObj Spi_DmaEventNum[SPI_HW_UNIT_CNT][4U] =
{
    [0U] =
    {
        {
            CSL_PDMA_CH_MCU_MCSPI0_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI0_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI0_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI0_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI0_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI0_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI0_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI0_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [1U] =
    {
        {
            CSL_PDMA_CH_MCU_MCSPI1_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI1_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI1_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI1_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI1_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI1_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI1_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI1_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [2U] =
    {
        {
            CSL_PDMA_CH_MCU_MCSPI2_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI2_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI2_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI2_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI2_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI2_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MCU_MCSPI2_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MCU_MCSPI2_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [3U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [4U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [5U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [6U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX,      /* txDmaEventNumber */
        },
    },
#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J784S4)
    [7U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [8U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [9U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX,      /* txDmaEventNumber */
        },
    },
    [10U] =
    {
        {
            CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX,      /* txDmaEventNumber */
        },
        {
            CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX,      /* rxDmaEventNumber */
            CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX,      /* txDmaEventNumber */
        },
    },
#endif
};

Regards

Tarun Mukesh

0 Jiang Liu 5 months ago in reply to Tarun Mukesh Puvvada

Prodigy 225 points

Thanks, I will look at MCAL driver for SPI

0 Jiang Liu 5 months ago in reply to Tarun Mukesh Puvvada

Prodigy 225 points

Hello,

After I looked at teh MCAL driver, I was trying to configure the second UDMA channel, it failed at configuring second RX udma channel,

I found it was assigned 4 channel for TX, but only 1 RX channel(see below screenshot). I would like to know if it is configured in sciclient_defaultBoardcfg_rm.c. I was trying to change the file (see attached code) to configure 3 RX channel, but it seems not affect it. by the way, my code runs on MCU2_1

0 Tarun Mukesh Puvvada 5 months ago in reply to Jiang Liu

TI__Mastermind 48486 points

Hello,

Jiang Liu said:
I found it was assigned 4 channel for TX, but only 1 RX channel(see below screenshot). I would like to know if it is configured in sciclient_defaultBoardcfg_rm.c. I was trying to change the file (see attached code) to configure 3 RX channel, but it seems not affect it. by the way, my code runs on MCU2_1

Yes the udma channel count is configured in sys config. You need to modify the resource in sysconfig tool and generate all the required files.

Regards

Tarun Mukesh

0 Tarun Mukesh Puvvada 5 months ago in reply to Tarun Mukesh Puvvada

TI__Mastermind 48486 points

You can follow FAQ

e2e.ti.com/.../faq-tda4vm-workflow-and-resource-allocation-build-flow-for-sysconfig-tool

0 Jiang Liu 5 months ago in reply to Tarun Mukesh Puvvada

Prodigy 225 points

Thanks, I will try it.

Jiang

0 Jiang Liu 5 months ago in reply to Jiang Liu

Prodigy 225 points

Hello,

The function multi-channel MCSPI with DMA is working, but it is not we expected, I have some questions:

we configured datasize is 16 bits,

1. it will switch to next channel after transfer 16 bits even we would like to transfer 32 bytes data for each channel, is there way to configure like after transferring 32 bytes data, then switch to next channel.

2. we would like to transfer 32 bytes data for each channel, each DMA trigger, each channel only transfers bits data, it stops, it is correct or can be configured as we expected:

like 16 bits data transfer of channel 1 ->(switch) ->16 bits data transfer of channel 2 -> (switch)-> 16 bits data transfer of channel 3-> (switch)-> 16 bits data transfer of channel 4->stop

we expect:

16 bits data transfer of channel 1 ->(switch) ->16 bits data transfer of channel 2 -> (switch)-> 16 bits data transfer of channel 3-> (switch)-> 16 bits data transfer of channel 4->next 16 bits data transfer of channel 1(switch) -> next 16 bits data transfer of channel 2 -> (switch)-> next 16 bits data transfer of channel 3-> (switch)-> next 16 bits data transfer of channel 4->....until 32 bytes data complete transfer

3. according to data sheet, it will switch "Rule 1: Only enabled channels (the MCSPI_CHCTRL_0/1/2/3[0] EN bit) can be scheduled for transmission
and/or reception", but what I observed: it will switch even MCSPI_CHCTRL_0/1/2/3[0] EN bit is not set, but the bit of FFER or FFEW in MCSPI_chCONFIG_0/1/2/3 is set

Thanks

Jiang Liu

0 Tarun Mukesh Puvvada 5 months ago in reply to Jiang Liu

TI__Mastermind 48486 points

Hello,

Jiang Liu said:
The function multi-channel MCSPI with DMA is working

Good to know that you made it working.

Jiang Liu said:
according to data sheet, it will switch "Rule 1: Only enabled channels (the MCSPI_CHCTRL_0/1/2/3[0] EN bit) can be scheduled for transmission
and/or reception", but what I observed: it will switch even MCSPI_CHCTRL_0/1/2/3[0] EN bit is not set, but the bit of FFER or FFEW in MCSPI_chCONFIG_0/1/2/3 is set

If FFER or FFEW is set in MCSPI_CHxCONF, the channel may still interact with the FIFO, causing unintended channel switching.

Workaround:

Clear FFER and FFEW bits for inactive channels if you don't intend to use them.Only one channel can have this bit field set each time. See in the below register snippet as well.

Ensure that the MCSPI_MODULCTR

L[1] MS bit is correctly set only for intended channels.

Regards

Tarun Mukesh

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TDA4VM: Multi UDMA configure for each MCSPI channel