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AM62L: Suggestions on the PCB Design

Chirag Rathod
Prodigy 30 points
Part Number: AM62L


Tool/software:

I am reaching out to request your assistance in determining the appropriate stencil thickness for the assembly of FCCSP (AM62LITE) component with the following specifications:
  • Ball Pitch: 0.50mm
  • Physical Pad Size: 0.25-0.35mm (Nominal 0.30mm)
  • Solder Pad Size (Footprint): 0.30mm
  • Solder Mask Size (Footprint):  0.40mm 
  • Solder Paste Size (Footprint): 0.30mm
  • Package Type: FCCSP (ANB373)
  • Minimum Stencil Thickness (Used by us): 4 Mils.
As per 0.30mm Solder pad size, the clearance between two solder pads edge to edge is 7.87 mils and If we used EVB footprint then Solder pad size is 0.254mm, which gives minimum stencil thickness of 3.7 mils. But We do not go less than 4 Mils.
 
As per 4 mils stencil thickness, We require 0.27mm Solder Pad Size. So If we go with 0.27mm Solder pad Size/Solder Paste Size and 0.30mm Solder Mask Opening then are there any difficulties while reflow soldering?

Thank you for your assistance. I look forward to your reply.

  • 0
    TI__Guru**** 197269 points

    Hello Chirag,

    Thank you for the query.

    Let me check with the team and comeback.

    Regards,

    Sreenivasa

  • 0
    TI__Mastermind 30140 points

    Hi,

    Remarks:
    1) Difference in pad size is small - but we are checking internally re difficulties while reflow soldering, and thicker stencil
     - EVM: 0.254mm (10 MIL)
     - Customer desired: 0.27mm (10.63 MIL)

    2) Is solder mask opening 0.30mm (11.81 MIL) wide enough for solder to wick down and around sides of each NSMD pad 0.27mm (10.63 MIL)?
     - The benefit of NSMD pads is more surface area of the pad attaching to the BGA
     - why not use larger SMO like 14 MIL (0.36mm)?
     
    3) JEDEC literature defines only minimum pad size for a given ball size
     b(nom) 0.3mm has min pad size of 0.20mm (SMD and NSMD)
     No max pad size is defined - it is dictated by the escape routing on same layer as pad
     
    4) In the AM62L EVM design, I increased pad size to 0.27mm (10.63MIL) and observed numerous Line to SMD Pin Spacing DRC violations
      Constraint value: 3.2 MIL
      Actual value:     2.9402 MIL

    In this board, traces escaping between pads on TOP layer are 3.2 MIL (minimum feasible trace width)
    This trace to pad spacing drove our EVM design to use a smaller pad size of 0.254mm (10 MIL) pad size dia (NSMD)
    Result is pad edge - 3.2MIL clearance - 3.2MIL trace - 3.2MIL clearance - pad edge

    Are you trying to escape pins on the same layer as the pads? Or maybe you have HDI routing rules?
    If you escape with pad size to 0.27mm (10.63MIL), the result is pad edge - 3MIL clearance - 3MIL trace - 3MIL clearance - pad edge

    That might cause PCB yield loss or more expensive PCB.

    Regards.