PROCESSOR-SDK-J784S4: Enable CPSW9g support in Uboot in PSDK10.1

Hi, 

SDK by default won't support CPSW9G at u-boot. 

You need to port older to new one by refering to the changes. 

Best Regards , 

Sudheer

Hello,

I am also interested in this. We build our code using Yocto, and we have decided to uprev both kernel (to 6.6) and U-Boot (to 2024.04).

I have checkout out tag 10.01.10 and applied our dts changes on top of that. It builds (with minor changes in am65-cpsw-nuss.c and Kconfig). Unfortunately the CPSW9G is not working in U-Boot. It was working fine with SDK8.2 + patches.

It would be good if someone can assemble what needs to be done to get it working again.

Most of the patches that Suman Anna produced for the 8.2 SDK seems to already be in place on tag 10.01.10. Is that correct? What more is needed to get CPSW9G working in U-Boot?

Regards,

/Bo

Hi

Bo Mellberg said:

Most of the patches that Suman Anna produced for the 8.2 SDK seems to already be in place on tag 10.01.10. Is that correct? What more is needed to get CPSW9G working in U-Boot?

Yes, Most of the changes available.
I think you need still additional changes to enable PSIL mapping for CPSW9G, SGMII enable form drivers and configure the required SerDes from board_late_init.

Best Regards,
Sudheer

Thanks Kumar,

The PSIL mappings are already in place. SGMII might be needed for those running that mode; we run RGMII on all our three ports.

When it comes to mapping the SERDES in board_late_init, I get the following error message:

U-Boot 2024.04-ti-g821fb6c64491 (Apr 09 2025 - 11:51:29 +0000)

SoC: J721E SR2.0 HS-FS
Model: Schneider Electric AS-P-3
DRAM: 2 GiB
/drivers/clk/clk-uclass.c:112-clk_get_by_index_tail() prop: returning err=-2
Core: 149 devices, 33 uclasses, devicetree: separate
MMC:
Loading Environment from SPIFlash... /drivers/mtd/spi/spi-nor-core.c:4001- spi_nor_soft_reset() jedec_spi_nor flash@0: Software reset enable failed: -524
/drivers/soc/ti/k3-navss-ringacc.c:1020- k3_nav_ringacc_init() k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
/drivers/soc/ti/k3-navss-ringacc.c:1025- k3_nav_ringacc_init() k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
/drivers/spi/cadence_qspi.c:1599-cadence_spi_mem_do_calibration() cadence_spi spi@47050000: Pattern not found. Skipping calibration
SF: Detected w25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In: serial@2800000
Out: serial@2800000
Err: serial@2800000
Failed to probe am65_cpsw_nuss driver
/drivers/clk/clk-uclass.c:112-clk_get_by_index_tail() prop: returning err=-2
/drivers/clk/clk-uclass.c:112-clk_get_by_index_tail() prop: returning err=-2
/drivers/clk/clk-uclass.c:112-clk_get_by_index_tail() prop: returning err=-2
/drivers/clk/clk-uclass.c:112-clk_get_by_index_tail() prop: returning err=-2
/drivers/phy/cadence/phy-cadence-sierra.c:1122-cdns_sierra_phy_probe() cdns,sierra serdes@5000000: PHY not found 0x7364 vs 0x0
Sierra init failed:-22
Net: /net/eth-uclass.c:454- eth_initialize() No ethernet found.
Hit any key to stop autoboot: 0
=>

Are there clocks that needs to be set up?

Regards,

/Bo

Hi,

Bo Mellberg said:

The PSIL mappings are already in place. SGMII might be needed for those running that mode; we run RGMII on all our three ports.

RGMII is not supported from CPSW9G on J784s4.

>> /drivers/phy/cadence/phy-cadence-sierra.c:1122-cdns_sierra_phy_probe() cdns,sierra serdes@5000000: PHY not found 0x7364 vs 0x0
Make sure SERDES MODULEs are enabled and device tree configuration also defined.
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y

Best Regards,
Sudheer

Hi,

Doredla Sudheer Kumar said:

RGMII is not supported from CPSW9G on J784s4.

Sorry, forgot to mention that we are on a J721e platform.

The serdes modules are defined and the CONFIGS are in place (Sierra, not Torrent since we have j721e):

Hi,

Please create a new thread with your configurations, this is related TDA4VH specific CPSW enable at u-boot.

Best Regards,
Sudheer