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SK-AM62P-LP: Enable DDRSS ECC

Raj Kumar
Intellectual 358 points

Part Number: SK-AM62P-LP

Tool/software:

Hello TI,

I am using the SK-AM62P-LP EVM and running Debian Trixie OS (version 10.00.00) along with the MCU+ SDK.
After reading the TRM, I have understood the functionality of the ECC (Error Correction Code) module. For functional safety, we would like to enable ECC for DDR4, and I have a few questions regarding this:

  1. DDR4 ECC is not enabled by default. Since we require it, we plan to enable it in the U-Boot configuration, rebuild it, and deploy it to the system. Could you please guide us through the procedure? Specifically, which flags or device tree nodes need to be changed to enable DDR4 ECC?

  2. We are initializing ECC for MCU_MSRAM (512 KB, with two endpoints: 8 and 21, each 256 KB), which are accessed through the MAIN_ECC_AGGR0 and processed by the R5 core.
    If we enable ECC for DDRSS, can both DDR ECC and MCU_MSRAM ECC run simultaneously without conflict?

Thank you,
RajKumar

  • 0
    TI__Mastermind 27546 points

    Hello Raj,

    Raj Kumar said:
    DDR4 ECC is not enabled by default. Since we require it, we plan to enable it in the U-Boot configuration, rebuild it, and deploy it to the system. Could you please guide us through the procedure? Specifically, which flags or device tree nodes need to be changed to enable DDR4 ECC?

    You can go through the link below on how to enable DDR ECC from Uboot

    https://software-dl.ti.com/processor-sdk-linux/esd/AM62PX/latest/exports/docs/linux/Foundational_Components/U-Boot/UG-DDRSS.html

    Raj Kumar said:

    If we enable ECC for DDRSS, can both DDR ECC and MCU_MSRAM ECC run simultaneously without conflict?

    Yes, there should not be any issues.

    Regards,

    Nihar Potturu.

  • 0 in reply to Nihar Potturu
    Intellectual 358 points

    Hello Nihar,

    Thank you for your response,

    I follow above link and changes has been done as per the document,(The changes that i done is i mentioned below)

    i added ti,ecc-enable; to &memorycontroller node inside a file path:${sdk_install_dir}/board-support/ti-u-boot-2024.04+git/arch/arm/dts/k3-am62-ddr.dtsi is this file path and modification is correct?

    #include "k3-am64-ddr.dtsi"
&memorycontroller {
	power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
			<&k3_pds 55 TI_SCI_PD_SHARED>;
	clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
	ti,ecc-enable;
};

    path:${sdk_install_dir}/board-support/ti-u-boot-2024.04+git/am62px_evm_r5_defconfig inside this path i added 

    CONFIG_K3_INLINE_ECC=y flag.
    with this changes i builded u-boot,after that i copied the req. files to the BOOT partition of the SD Card and while booting i entered into the u-boot mode and i tested the ddrss ecc_err it was showing ecc not enabled.
    Can you help me out why it is happening like this.

    I mention the screenshot of u-boot.cfg file of r5,there also ecc was enabled .
    Thank you,
    RajKumar.
  • 0 in reply to Raj Kumar
    Intellectual 358 points

    Hello Nihar,

    When can I expect a response regarding the above thread?

    To add to the discussion, I tested the DCC example code located at:
    ti/mcu_plus_sdk_am62px_10_00_00_14/examples/drivers/ddr/ddr_ecc_test_main_esm,
    which verifies single-bit and double-bit error detection.

    The code worked as expected in OSPI mode, and the interrupt source was correctly triggered. However, when I switched to SD card boot mode by symlinking to the binary file, the board failed to boot.

    Is it necessary to enable DDR ECC in U-Boot for this test to run successfully?

    Looking forward to your response.

    Best regards,
    Raj.