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AM37x mcbsp connections

Still I didnt get any reply...Please give me your reply asap.

 

Thanks

TQR

its been two three days but I didnt get any reply for this post..

please reply to my queries and help me to complete the task on time.

 

thanks

tauqueer

Hi,

I am using TMDSEVM3730 as our development board and want to connect my FPGA board with available mcbsp port of the 37x board.

I just want to loopback the mcbsp signal from my fpga means I want to take clkx , syncx and DTX from 37x mcbsp and rout them back to mcbsp again on clkr, syncr and DR respectively of same mcbsp (MCBSP1) at the same time without any delay.

I just want to confirm that will this logic work??

if  yes then in which mode I should configure the mcbsp1?

I am thinking of configuring it in transmit in master in receive in slave mode.

Please guide me with the right approach to get the required logic.

thanks

tauqueer

 

 

  • Tauqueer

    You configuration should work.

    If you do not require the RX and TX paths to be asynchronous then you could use the 4-pin mode (TX and RX paths share CLKX and FSX) and save pins.

    If you could provide more details on what you are trying to implement?

      Paul 

  • PaulM,

    Based on your feedback I am using 4-pin  mode and I am using mcbsp2 for this purpose.My Rx and Tx are not asynchronous.

    Actually I want to implement a cryptographic algorithm in my external device which will have mcbsp interface to communicate with processor.

    but right now I just want to XOR the data receive on TX and want to rout them back on RX of mcbsp2.

    Is it possible to implement a AES/DES core with same interface later without changing any thing in the driver side? I mean I ll receive the data on TX line and ll do some processing and rout them back to RX and i want to use the same CLKX and FSX.

     

    Thanks

    Tauqueer

     

     

     

  • Tauqueer

    The McBSP is just a communication interface and does not care what data you put in the packets.

    Using a 4-pin interface will mean that a data word will be received for each word transmitted. So assuming that the there will be some latency for the slave device to process the data it will have to return one or more words to the master that contain no valid content. At the end of the transfer it will be necessary for the master to send dummy data in order for the slave to return any pending data. If this is the case then your code will have to implement some mechanism to control this.

    Using a 6-pin mode would allow the target device to control when it sends the returned data and avoid the need for they type of padding/control mentioned above.

      Paul