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C6678 performance

Ya D
Intellectual 485 points


Hi,

It says here: TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor (Rev. B) (sec. 2.2):

"Each C66x .M unit can also perform one the following floating-point operations each clock cycle: one, two, or four
single-precision multiplies or a complex single-precision multiply."

In order to do 4 SP multiplications you need (2*32*4=256bit) of data. However, to my understanding, bus width
to the register file is 64 bits. So it seems that the 4 SP multiplications per cycle is more then it can handle.

Am I missing something?

 

Thank you.

  • 0
    TI__Guru* 84110 points

    Ya D,

    That would be very powerful to have a DSP built from processing elements that can access 256 bits of data in a single cycle. And have it run at up to 1.25GHz. And have each DSP core implement 2 of those processing elements so it can do 8 of those SP multiplies in a single cycle. And even better to have 8 of those DSP cores for a total of 16 of those .M units on one chip.

    TI is a conservative company. We may make bold claims in our datasheet, but we tell the truth.

    You cannot figure out all the capabilities of one of these devices by reverse engineering the datasheet. We do not supply enough information to allow you to design your own, but we supply enough information for you to know what you can do with it.

    The next document you need to study is the C66x CPU & Instruction Set Reference Guide. It describes greater detail than the datasheet so you can learn more about the CPU architecture and the various instructions. Search that Ref Guide for "four floating point multiplies" without the quotes to find out if there is an instruction that does what you have quoted above. You can find that document and others at the TMS320C6678 Product Folder, click on Technical Documents.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.