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Original question:

DRA829J: DRA829

DRA829J: Debug Interface documentation of the DRA829

Ralf Moehring
Prodigy 60 points
Part Number: DRA829J
Other Parts Discussed in Thread: DRA829

Tool/software:

I am looking for the Debug Interface documentation of the DRA829 chip.
We are able to read the JTAG ID (0x6BA00477). But we are not able to read or write any other Debug Registers or Access Points.
Can you provide us with the information of the Debug Interface:
* Access Point Numbers
* Core Order
* IcePick !? Info
* Initial Setup of the MCU
* Handling of the 2EMU Pins

  • 0
    TI__Mastermind 21215 points

    Hello,

    The TRM in this targets describing features not providing information necessary for an implementation.  The information to do that is spread across many other documents (ex ARM coresight debug and arm core documents).   The DRA829 does implement a coresight compliant ROM table which can be scanned to provide the component information.

    For generic debug you will find a standard APB-AP on DAPBUS APSEL-1 (for debug component control, with a rom table at apb:0x0) and an AXI-AP (for system bus access) at APSEL-2.   This is accessed via a standard ARM DP.   An ice-pick-m is in parallel but is not needed for debug, it only needed if bsdl is desired (EMU0=1, EMU1=0 as seen in the compliance section of the BSDL file for the CPU).

    A number of 3rd party and community JTAG tools already support from Open-OCD, CCS, Seggar, Isystems, GHS, Lauterbach, etc...

    Regards,
    Richard W.