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EMIF16 Sysclkout

Bonjour,

 

Can we guarantee the timing of EMIF16 data vs. Sysclkout? even if skew between signals is not guaranteed should we expect any drift in this skew? eg. are the timing generated from the same DPLL? the idea is to resync EMIF16 data with respect to this clock (or another one...)

 

Regards

 

  • I'm not sure which specific part you're asking about so I can't give you a specific answer but generally the EMIF16 and the SYSCLKOUT timing is not specified against the other.  Although they are usually derived from the same clock source the skew is not  guaranteed by design.  In some components there is a EMIF clock output which can be used for synchronous EMIF accesses but in most cases EMIF is considered an asynchronous interface.