TDA3MV: DDR3 related fault issue

Ted Huh

Intellectual 2975 points

Part Number: TDA3MV

Tool/software:

Hi Team,

My customer has some issue while they are using TDA3MVRBFABFRQ1

with 2pcs DDR3(K4B4G1646E-BNCB)

Here's the log they get.

What can be the cause of this problem?

if you need more data to analyze this please let me know.

Regards,

Ted

5 months ago

0 Kevin S 5 months ago

TI__Mastermind 38200 points

Hi,

Is this a new design, or existing design?

How many boards have been built / tested, and how many show the issue?

Does the failure occur every boot cycle, or just sometimes?

Regards,
Kevin

0 Ted Huh 5 months ago in reply to Kevin S

TI__Intellectual 2975 points

The board is on the validation state.

they built 300boards, and 5 board has an issue.

once the issue happens, it happens every boot cycle.

Regards,

Ted

0 Ted Huh 5 months ago in reply to Ted Huh

TI__Intellectual 2975 points

Hi Kevin,

Can you take a look at this?

Regards,

Ted

+1 Kevin S 5 months ago in reply to Ted Huh

TI__Mastermind 38200 points

Hi,

Do you have the register settings they are using , specifically the array they are using to setup the PHY registers? (example below)

Regards,
Kevin

const unsigned int DRA75x_DDR3L_532MHz_TI_EVM_revH_emif1_ext_phy_regs [] = {

0x04040100,

0x006B006B,

0x00320032,

0x00600060,

0x00400040,

0x00800080,

0x40010080,

0x08102040,

0x00000000,

0x00000077

};

0 Ted Huh 4 months ago in reply to Kevin S

TI__Intellectual 2975 points

Fullscreen TDA3x_DDR3L_532MHz_D3_RVP_rev1.txt Download

    SDRAM_TIM_1 = 0xCEEF266BU;
    SDRAM_TIM_2 = 0x30BF7FDAU;
    SDRAM_TIM_3 = 0x407F8BA8U;

    SDRAM_REF_CTRL = 0x00001035U;
    SDRAM_REF_CTRL_INIT = 0x000040F1U;
    SDRAM_CONFIG = 0x61851BB2U;

    EMIF_PHY_READ_LATENCY = 0xEU;
    EMIF_PHY_INVERT_CLKOUT = 0x1U;
    EMIF_PHY_HALF_DELAY_MODE = 0x1U;
    EMIF_PHY_DQ_OFFSET = 0x40U;
    EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;

    DISABLE_READ_LEVELING = 0x1U;
    DISABLE_READ_GATE_LEVELING = 0x1U;
    DISABLE_WRITE_LEVELING = 0x1U;

    /* EXT_PHY_CTRL_xx are used only in case of  HW_LEVELING_ENABLED  =  0*/
    /* EMIF_PHY_FIFO_WE_SLAVE_RATIO (RD_DQS_GATE) */
    EXT_PHY_CTRL_2 = 0x07000075U;
    EXT_PHY_CTRL_3 = 0x0700007AU;
    EXT_PHY_CTRL_4 = 0x07000076U;
    EXT_PHY_CTRL_5 = 0x07000078U;
    EXT_PHY_CTRL_6 = 0x07000700U;

    /* EMIF_PHY_RD_DQS_SLAVE_RATIO */
    EXT_PHY_CTRL_7 = 0x0000003BU;
    EXT_PHY_CTRL_8 = 0x0000003BU;
    EXT_PHY_CTRL_9 = 0x00000040U;
    EXT_PHY_CTRL_10 = 0x0000003BU;
    EXT_PHY_CTRL_11 = 0x00000000U;

    EXT_PHY_CTRL_12 = 0x01A3005DU;
    EXT_PHY_CTRL_13 = 0x00E0005FU;
    EXT_PHY_CTRL_14 = 0x03160061U;
    EXT_PHY_CTRL_15 = 0x005E0066U;
    EXT_PHY_CTRL_16 = 0x02320130U;

    /* EMIF_PHY_WR_DQS_SLAVE_RATIO */
    EXT_PHY_CTRL_17 = 0x018B00045U;
    EXT_PHY_CTRL_18 = 0x00C80047U;
    EXT_PHY_CTRL_19 = 0x02FE0049U;
    EXT_PHY_CTRL_20 = 0x0046004EU;
    EXT_PHY_CTRL_21 = 0x02320130U;

Here's their register setting. When they did device swap and then on both board it worked well, so they stopped the investigation.

Assumption : SMT issue

Regards,

Ted

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TDA3MV: DDR3 related fault issue