DRA821U: How to get CPU running frequency?

Hi Kyle,

Understood that we need to change the default superset SDK frequency settings which is for -T 2GHz speed to our -C 750MHz speed.

Q1: does -C speed part support 2GHz ? or it runs 750MHz even the default setting is 2GHz?

Q2: are DDR and PCIe data rates impacted by this core frequency settings (-C speed vs -T speed) ? my understanding is not, correct?

Q3: how much power consumption difference between -C speed and -T speed at same resource workload?

Thanks

Max

Hi Max,

1. It will run at whatever frequency is set by software.  However, considering the part is meant to operate at max 750 MHz, you may see functional problems/crashes if software configures for 2 GHz.

2. Refer to Speed Grade table in the datasheet.  PCIe and LPDDR are not reduced based on speed grade.  R5F is limited to 500 MHz.

3. Will pull in another colleague to help with this one.

Regards,

Kyle

Hi Kyle,

Thanks for the info. We're using TI Yocto project's devtool to patch and build custom image. Can you tell me the recipe name in which I need to modify the configuration file packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h?

Thanks,

Charles

Hi Jared,

Thanks for your reply. I created a workspace u-boot-ti-staging, but I couldn't find the file sbl_soc_cfg.h file in the workspace to patch.

build/workspace/sources/u-boot-ti-staging$ find -name sbl_soc_cfg.h -print
build/workspace/sources/u-boot-ti-staging$

Hi Jared,

Sorry for the confusion. I mentioned sbl_soc_cfg.h just because Kyle provided reference suggests to patch it (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1227640/faq-tda4vm-tda4vl-tda4al-tda4vh-dra821-how-can-we-make-the-jacinto-sdk-compatible-for-device-variants-yxz). Based on your feedback, I think I should modify SPL boot instead. What I need is to change A72 CPU frequency from default 2GHz (superset chip -T speed grade) to my chip graded speed (I'm using -C speed 750MHz).

Can you tell me which file should I patch so my Linux image can run at 750MHz rather than the default 2GHz?

Thanks,

Charles

Hi Charles,

Can you look at the following threads/FAQs?

• https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1060392/tda4vm-how-to-change-the-cpu-frequence/3944368#3944368
• https://e2e.ti.com/support/processors-group/processors/f/processors-forum/997678/faq-dra821u-how-to-change-the-frequency-of-a72-and-r5f-cores-and-disable-one-a72-core 

Best,
Jared

Hi Jared,

Thanks for the info. Where can I find the device tree binding document for A72 core?

It looks like my dts file (SDK 10.00.08) is different from the u-boot patch you provided in the link e2e.ti.com/.../faq-dra821u-how-to-change-the-frequency-of-a72-and-r5f-cores-and-disable-one-a72-core.

For the assigned-clock-rates property, u-boot patch shows two integer values while in my device tree file, there are 3 integer values.

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 6bfc322da2..059fdf26aa 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -33,7 +33,7 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
- assigned-clock-rates = <2000000000>, <200000000>;
+ assigned-clock-rates = <400000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;

my device tree:

                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>, <&k3_clks 4 1>, <&k3_clks 202 2>;
                clock-names = "gtc_clk", "msmc_clk", "arm_clk";
                assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>, <&k3_clks 323 0>;
                assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
                assigned-clock-rates = <1000000000>, <200000000>, <1000000000>;
 

Which value is the real CPU frequency to use? Where's the document?

Thanks,

Charles

Hi Charles,

Charles Mao said:

Thanks for the info. Where can I find the device tree binding document for A72 core?

The A72 falls under: https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.yaml 

Charles Mao said:

Which value is the real CPU frequency to use? Where's the document?

The clock identities can be found here: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html 

Clock "202 2" corresponds to: DEV_A72SS0_CORE0_0_ARM_CLK_CLK, so setting that clock to 750 MHz would work.

The following are the other clock identities:

• 61 1: DEV_GTC0_GTC_CLK
• 4 1: DEV_A72SS0_CORE0_MSMC_CLK
• 323 0: DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK

Best,
Jared