Maximum I/O Speed

Hi Alistair,

In general, the maximum PRU parallel capture input clock is determined by the PRU firmware.  Please note there is no FIFO for parallel capture.  The firmware will therefore need to keep up with the data rate. 

Some sort of "flag" is also needed so the PRU knows when it has new data.  For example, the PRU could sample the clock signal as a flag (pru<n>_pru_r31[16]).  Or the PRU could use one of the data signals (pru<n>_pru_r31[15:0]) as a valid signal that switches slower than the clock rate.  Whatever flag is used, the PRU needs to have enough processing time to sample the flag signal at both high and low states (and complete whatever other tasks the PRU needs to do).

The tightest loop for sampling the signal, determining if the line toggled, and simply writing the captured data to the same PRU DRAM address each iteration is 5 PRU cycles.  Therefore, the max flag speed the PRU can handle with the least amount of overhead is 20 MHz (200 MHz / 5 / 2 = 20 MHz, or PRU clock / 5 PRU cycles / 2 samples per flag clock).  Note that adding additional PRU processing / instructions to this loop will  require a slower flag.

Regards,
Melissa