TDA4VEN-Q1: Nanya DDR adaptation issues

xie jc

Part Number: TDA4VEN-Q1

Tool/software:

Dear TI's experts,

RTOS Version: SDK10.1

We are trying to adapt to the Nanya 2G DDR(NT6AN512T32AC-J1H) on our own TDA4VEN board, but it is not starting properly and only SBL has partial printing.

I also uploade the syscfg and DDR data manuals.Please help me confirm if the DDR parameter configuration is correct？

0246.all.zip

8(16bit),16(32bit),32(32bit)Gb LPDDR4 auto.PDF

Regards.

5 months ago

0 Biao Li 5 months ago

TI__Expert 6370 points

Hi Weizhen,

can you help try below configuration?

all (19).zip

BR,

Biao

0 xie jc 5 months ago in reply to Biao Li

Expert 2160 points

Hi Biao,

The configuration is useful.The current startup can boot into the kernel.

Also, if I need to adapt to 4G Nanya DDR(NT6AN1024F32AC-J2H), what modifications do I need to make to the configuration (in the same data manual).

Regards.

0 Biao Li 4 months ago in reply to xie jc

TI__Expert 6370 points

Hi Weizhen,

pls have a try below config, I have changed some parameters to help for your mem test error issue, pls have a try, if still have the mem test error, pls upload the log.

all (20).zip

BR,

Biao

0 xie jc 4 months ago in reply to Biao Li

Expert 2160 points

Hi Biao，

The issue of memtester failure still occurs when using the latest configuration.

Fullscreen memtester_test_failed.txt Download

root@j722s-evm:~# memtester 1G
memtester version 4.6.0 (64-bit)
Copyright (C) 2001-2020 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

pagesize is 4096
pagesizemask is 0xfffffffffffff000
want 1024MB (1073741824 bytes)
got  1024MB (1073741824 bytes), trying mlock ...locked.
Loop 1:
  Stuck Address       : ok
  Random Value        : ok
  Compare XOR         : ok
  Compare SUB         : ok
  Compare MUL         : ok
  Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : ok
  Block Sequential    : ok
  Checkerboard        : testing  49FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x0000000019815b70.
FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x0000000019815b78.
FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x0000000019815b80.
FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x0000000019815b88.
FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x0000000019815b90.
FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x0000000019815ba0.
  Bit Spread          : testing  66FAILURE: 0xa000000000000000 != 0xa0ff000000ff0000 at offset 0x000000000bd12c70.
FAILURE: 0x5fffffffffffffff != 0x5f00ffffff00ffff at offset 0x000000000bd12c78.
FAILURE: 0xa000000000000000 != 0xa0ff000000ff0000 at offset 0x000000000bd12c80.
FAILURE: 0x5fffffffffffffff != 0x5f00ffffff00ffff at offset 0x000000000bd12c88.
FAILURE: 0xa000000000000000 != 0xa0ff000000ff0000 at offset 0x000000000bd12c90.
FAILURE: 0xa000000000000000 != 0xa0ff000000ff0000 at offset 0x000000000bd12ca0.
  Bit Flip            : testing  35FAILURE: 0x0000000000000010 != 0x00ff000000ff0010 at offset 0x000000001b021a30.
FAILURE: 0xffffffffffffffef != 0xff00ffffff00ffef at offset 0x000000001b021a38.
FAILURE: 0x0000000000000010 != 0x00ff000000ff0010 at offset 0x000000001b021a40.
FAILURE: 0xffffffffffffffef != 0xff00ffffff00ffef at offset 0x000000001b021a48.
FAILURE: 0x0000000000000010 != 0x00ff000000ff0010 at offset 0x000000001b021a50.
FAILURE: 0x0000000000000010 != 0x00ff000000ff0010 at offset 0x000000001b021a60.
  Walking Ones        : ok
  Walking Zeroes      : ok

Loop 2:
  Stuck Address       : testing   0FAILURE: possible bad address line at offset 0x0000000016546880.
Skipping to next test...
  Random Value        : FAILURE: 0xfbdfe1867ef75032 != 0xfbfee1867e2f5032 at offset 0x0000000004115040.
FAILURE: 0xb7edc512fff7e095 != 0xb7dfc512fff7e095 at offset 0x0000000004115048.
FAILURE: 0xfcbfc74327fec4d0 != 0xfcedc74327f7c4d0 at offset 0x0000000004115050.
FAILURE: 0x5dcf4c62e7ba3fdc != 0x5dbf4c62e7fe3fdc at offset 0x0000000004115058.
FAILURE: 0x37c312ce1fff3993 != 0x37cf12ce1fba3993 at offset 0x0000000004115060.
FAILURE: 0x9e7eed43f3be9fac != 0x9ec3ed43f3ff9fac at offset 0x0000000004115068.
FAILURE: 0xefd33a5ceeadfe45 != 0xef7e3a5ceebefe45 at offset 0x0000000004115070.
FAILURE: 0xe30045072fff3262 != 0xe3d345072fad3262 at offset 0x0000000004115078.
  Compare XOR         : ok
  Compare SUB         : ok
FAILURE: 0x82008def98c2bcb8 != 0x82c28def9815bcb8 at offset 0x0000000007445038.
  Compare MUL         :   Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : testing  18FAILURE: 0xff00ffffff00ffff != 0xffffffffffffffff at offset 0x0000000008fb7dc0.
FAILURE: 0x00ff000000ff0000 != 0x0000000000000000 at offset 0x0000000008fb7dc8.
FAILURE: 0xff00ffffff00ffff != 0xffffffffffffffff at offset 0x0000000008fb7dd0.
FAILURE: 0x00ff000000ff0000 != 0x0000000000000000 at offset 0x0000000008fb7dd8.
FAILURE: 0xff00ffffff00ffff != 0xffffffffffffffff at offset 0x0000000008fb7de0.
FAILURE: 0xff00ffffff00ffff != 0xffffffffffffffff at offset 0x0000000008fb7df0.
  Block Sequential    : ok
  Checkerboard        : testing  16FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x000000000e8634f0.
FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x000000000e8634f8.
FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x000000000e863500.
FAILURE: 0xaaaaaaaaaaaaaaaa != 0xaa55aaaaaa55aaaa at offset 0x000000000e863508.
FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x000000000e863510.
FAILURE: 0x5555555555555555 != 0x55aa555555aa5555 at offset 0x000000000e863520.
  Bit Spread          : testing  14FAILURE: 0x0000000000014000 != 0x00ff000000fe4000 at offset 0x000000000e491ff0.
FAILURE: 0xfffffffffffebfff != 0xff00ffffff01bfff at offset 0x000000000e491ff8.
FAILURE: 0x0000000000014000 != 0x00ff000000fe4000 at offset 0x000000000e492000.
FAILURE: 0xfffffffffffebfff != 0xff00ffffff01bfff at offset 0x000000000e492008.
FAILURE: 0x0000000000014000 != 0x00ff000000fe4000 at offset 0x000000000e492010.
FAILURE: 0x0000000000014000 != 0x00ff000000fe4000 at offset 0x000000000e492020.
  Bit Flip            : testing  52FAILURE: 0xffffffffffffffbf != 0xff00ffffff00ffbf at offset 0x0000000018058ab0.
FAILURE: 0x0000000000000040 != 0x00ff000000ff0040 at offset 0x0000000018058ab8.
FAILURE: 0xffffffffffffffbf != 0xff00ffffff00ffbf at offset 0x0000000018058ac0.
FAILURE: 0x0000000000000040 != 0x00ff000000ff0040 at offset 0x0000000018058ac8.
FAILURE: 0xffffffffffffffbf != 0xff00ffffff00ffbf at offset 0x0000000018058ad0.
FAILURE: 0xffffffffffffffbf != 0xff00ffffff00ffbf at offset 0x0000000018058ae0.
  Walking Ones        : testing  68                                                                                                                    testing  75

Best Regards.

0 Xingyu Zhu 4 months ago in reply to xie jc

TI__Expert 4275 points

Hi Kevin,

Please check below test result.

nanya_memory_test_result.rar

Debug approach:

Register Dump
Memtester log
MR values dump
Training value dump
Eye Diagram

0 xie jc 3 months ago in reply to Xingyu Zhu

Expert 2160 points

Hi Xingyu,

I'm sorry I haven't updated the status of this thread for a long time. Because we are currently in communication with Nanya's engineers regarding the details of DDR parameters and conducting bench pressure testing. Now synchronize the current situation.

All modifications were made based on the all(20).zip provided by libiao earlier.

1)DDRSS_PHY_67_DATA 0x00000004 -> 0x00000104

DDRSS_PHY_323_DATA 0x00000004 -> 0x00000104

DDRSS_PHY_579_DATA 0x00000004 -> 0x00000104

DDRSS_PHY_835_DATA 0x00000004 -> 0x00000104

2)Modify DQ ODT from 48ohm to 40ohm.

Based on the above two modifications, we performed a "memtester 1G" test on the test bench for 392 loops. During the test, we found that loops 52 and 233 had failed errors, with the following log: "Walking Zeroes: testing 13Failure: 0x00000200000002000!=0x0000000 2000 at offset 0x00000001ad5f1".

In this situation, I have added the following modification. Currently, the memtester on the test bench has tested 210 loops without reporting any errors, and the testing is still in progress

3)Modify CA ODT from 80ohm to 60ohm.

Best Regards.

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TDA4VEN-Q1: Nanya DDR adaptation issues