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selecting SPI flash for boot with DM8168

Andrew Dyer
Intellectual 650 points


I can't seem to find anything that tells me what the requirements are for a SPI flash device to boot with on a DM8168.  I looked in the datasheet, TRM, processor wiki, and e2e forums.

I see that spectrum digital used W25X32VSFIG Winbond Electronics Corp. on the EVM design.  I am looking in particular at Micron devices on their 'product longevity program' list and trying to see what devices will work, but it's unclear without knowing what the DM8168 bootloader code expects.

  • 0
    TI__Guru 64540 points

    The requirements of the SPI flash are indicated in the DM8168 Technical Reference Manual in Chapter 3 regarding ROM Code Memory and Peripheral Booting.  Specifically, in Section 3.7.5, the TRM talks about the SPI flash characteristics.

    • Supports 12 MHz clock (50% duty cycle)

    • Supports only SPI Mode 3 (clock polarity = 1, clock phase = 1)

    • Supports only 24 bit addressable EEPROMs

    • Supports only 4-pin SPI mode (CS, CLK, Serial Input, Serial Output)

    • The boot devices must be connected to channel 0 and must support the read command (03h)

    • The boot image is copied into internal memory and then executed

    Furthermore, taking from the TRM document:

     

    The ROM Code initializes the SPI controller, pin muxing and clocks for communicating with the SPI device. The controller is initialized in Mode 3 and the clock is setup to operate at 12 MHz. There is no specific device identification routine that is executed by the ROM code to identify whether a boot device is preset or not. If no SPI device is present, the sector read will return only 0xFFFFFFFF and the SPI boot will be treated as failed.

  • 0 in reply to BrandonAzbell
    Intellectual 650 points

    Brandon, thanks for the reply.

    I'm a bit confused as I don't see that section.  I am looking at "TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual" SPRUGX8 dated 1 July 2011. Section 3 is for Power Management.  There is a section 25 which is titled 'ROM Code Memory and Peripheral Booting'.  Section 25.7.1 mentions SPI EEPROMs but gives no details.

     

    Could you post a link to the doc you are referring to?

  • 0 in reply to Andrew Dyer
    TI__Guru 64540 points

    Wow!  This makes me wonder what I was looking at.  Certainly the evidence would suggest I was off in la-la land.

    I will bring this to the attention of the product group to see if we can get this addressed in a refresh of the documentation.

  • 0
    TI__Mastermind 25055 points

    Andrew,

    Sorry for the missing info.  We also noticed this and a new SPI subsection will be added to the Memory Booting section in the next rev of the Device TRM.  It is copied below.

    Regards,
    Marc

     SPI

    SPI EEPROMs or SPI flashes have an EEPROM or NOR flash backend and they connect to the device using the serial SPI protocol.

    These typically devices operate in three stages – the command stage, the address stage and the data transfer stage. The command is usually an 8 bit value followed by the address (depending on the size of the device) followed by the data to be read or written.  Because of the need for fewer pins, these devices are comparatively inexpensive, easy for board layout, and are the devices of choice when cost, complexity and form factor are critical considerations.

     Initialization and detection

    The ROM Code initializes the SPI controller, pin muxing and clocks for communicating with the SPI device. The controller is initialized in Mode 3 and the clock is setup to operate at 12 MHz. There is no specific device identification routine that is executed by the ROM code to identify whether a boot device is preset or not. If no SPI device is present, the sector read will return only 0xFFFFFFFF and the SPI boot will be treated as failed.

    SPI Read Sector Procedure

    The ROM Code reads SPI data from the boot device in 512 byte sectors. For each call to the SPI Read Sector routine, the SPI Read Command (0x03) is sent along with the 24 bit start address of the data to be read. From the next iteration onwards, a dummy value is transmitted on the master out line and the data is received on the master in line. This needs to be done because SPI protocol always operates in full duplex mode. The dummy data transmitted by the ROM is the Read Command appended to the start address. The data from the boot device is received MSB first.  As the Cortex-A8 is a little-endian processor, and SPI operates in a big-endian format, this means that while writing to the flash, care needs to be taken to write the image in a big-endian format. This avoids doing the endian conversion at boot time, thus improving boot performance.

    Pins used

    The list of device pins that are configured by the ROM in the case of SPI boot mode are shown in the table below. Please note that all the pins might not be driven at boot time.  The default state of the other SPI chip select pins could be low at POR, so care must be taken if any other devices are connected to CS[1], CS[2] or CS[3]. External logic must be used to ensure that the chip select to these devices are not enabled by default.

    Table: Pins used for SPI boot

    Signal name     Pin used

    cs                     spi_scs[0]
    miso                 spi_d[0]
    mosi                 spi_d[1]
    clk                    spi_sclk

     Features:

     Supports 12 MHz clock (50% duty cycle)
     Supports only SPI Mode 3 (clock polarity = 1, clock phase = 1)
     Supports only 24 bit addressable EEPROMs
     Supports only 4-pin SPI mode (CS, CLK, Serial Input, Serial Output)
     The boot devices must be connected to channel 0 and must support the read command (03h)
     The boot image is copied into internal memory and then executed.