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TDA4VM: How to check reset reason in J7200 device

Part Number: TDA4VM

Tool/software:

Dear TI,

Could you let me know how to check reset reason ?

When I check CTRLMMR_WKUP_RST_STAT Register, it is 0x00010001 even after power on reset

root@j7200-evm:~# devmem2 0x43018178
/dev/mem opened.
Memory mapped at address 0xffffb348f000.
Read at address 0x43018178 (0xffffb348f178): 0x00010001

Is there any register which I can distinguish below reset reason ?

- warm reset

- power on reset 

- watchdog reset

BR

Jace

  • Hi Jace,

    In the TRM CTRLMMR_WKUP_RESET_SRC_STAT gives the reasons for reset.

    - Keerthy

  • Hi Keerthy

    Thank you for the information.

    Could you also let me know how to check Watchdog reset reason ?

    BR

    Jace

  • Hi Jace,

    No. I do not see anything in the TRM. That said I am double checking with hardware experts if we have something. I will keep you posted
    as soon as i receive feedback from them.

    - Keerthy

  • Hi Jace,



    You could monitor bit19 of the same register for cold_out_rst this is set for watchdog reset as suggested by our hardware experts.

    - Keerthy

  • Hi Keerthy.

    I tested watchdog with TDA4VM board.

    I triggered watchdog by wdctl and the board reboot after 60 seconds

    But when I check 0x43000050, all bits were '0'.

    root@j7200-evm:~# wdctl
    [   19.339943] watchdog: watchdog0: nowayout prevents watchdog being stopped!
    [   19.346838] watchdog: watchdog0: watchdog did not stop!
    Device:        /dev/watchdog0
    Identity:      K3 RTI Watchdog [version 0]
    Timeout:       60 seconds
    Pre-timeout:    0 seconds
    Timeleft:      60 seconds
    FLAG           DESCRIPTION           STATUS BOOT-STATUS
    KEEPALIVEPING  Keep alive ping reply      1           0
    root@j7200-evm:~#
    U-Boot SPL 2023.04-ti-gd2612223375a (Mar 13 2024 - 19:15:42 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    Trying to boot from MMC2
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Loading Environment from nowhere... OK
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
    NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
    I/TC:
    I/TC: OP-TEE version: 4.1.0-51-g012cdca49 (gcc version 11.4.0 (GCC)) #1 Tue Jan 30 10:48:03 UTC 2024 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: GIC redistributor base address not provided
    I/TC: Assuming default GIC group status and modifier
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot
    
    U-Boot SPL 2023.04-ti-gd2612223375a (Mar 13 2024 - 19:15:42 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
    Detected: J7X-BASE-CPB rev A
    Detected: J7X-VSC8514-ETH rev E2
    Trying to boot from MMC2
    am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    
    
    U-Boot 2023.04-ti-gd2612223375a (Mar 13 2024 - 19:15:42 +0000)
    
    SoC:   J7200 SR2.0 GP
    Model: Texas Instruments K3 J7200 SoC
    Board: J7200X-PM2-SOM rev E8
    DRAM:  2 GiB (effective 4 GiB)
    Core:  85 devices, 32 uclasses, devicetree: separate
    Flash: 0 Bytes
    MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
    Loading Environment from nowhere... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
    Detected: J7X-BASE-CPB rev A
    Detected: J7X-VSC8514-ETH rev E2
    Net:   eth0: ethernet@46000000port@1
    Hit any key to stop autoboot:  0
    => md.l 0x43000050 1
    43000050: 00000000                             ....
    => md.l 0x43002050 1
    43002050: 00000000                             ....
    => md.l 0x43000050 1
    43000050: 00000000

    Could you double check watchdog function with EVM.

    BR

    Jace

  • Okay. I will let the hardware experts know about this behaviour. Other than this bit we do not have any other way.

    Best Regards,

    Keerthy 

  • Hi,

    If you have access to JTAG or a debugger can you read the same via M3 register & double confirm that bit19 reads 0?

    - Keerthy

  • Hi Keerthy.

    After watchdog reset, the board boot  up correctly. So I can read registers in Uboot or linux console.

    Why do you want me to read values via JTAG or another debugger ?

    Is these registers only possible to read via JTAG ?

    What is M3 register ? Could you let me know the register name and address ?

    BR

    Jace

  • I don't understand. Can you clarify the watchdog you are looking for?
    Inside the SoC, the WWDRTI-generated go to CPU cores and the ESM. The ESM, if configured, could generate a signal to the PMIC which would, in turn, reset the SoC. I don't think that the WWDRTI has an ability to reset the SoC directly.

    Kevin

  • Hi Kevin.

    Sorry for the late response.

    Actually, I don't know the exact sequence of watchdog in TDA4VM board.

    Now I got to know that PMIC triggers watchdog reset.

    Than how can I check that the board is reset by watchdog reset after boot up ?

    And could you explain the watch dog reset sequence more detail ?

    What is ESM ?

    BR

    Jace

  • what PDN are you using?

    Kevin

  • Hi Kevin.

    What is PDN ?

    Our board is based on TDA4VM and has a nearly identical configuration.

    So it's OK to explain the sequence for TDA4VM.

    BR

    Jace