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Questions using GPMC to interface with Spansion NOR without nAVD/ALE line

Hi,

The board I'm using:

I'm using the DM816x/C6A816x/AM389x Evaluation Module (EVM). The board interface with a daughter board (816x/389x EXPANSION I/O DAUGHTER CARD).

Confusion:

I'm trying to use GPMC to interface with the Spansion NOR (S29GL512P11TFI010) on the daughter board. I looked at the TRM for AM389x (Literature Number:SPRUGX7), in Section 9.4.1.4 GPMC Configuration for Asynchronous Read Access, Table 9-48 shows the memory side read timings, but this is assuming the asynchronous NOR memory to have the ADV/ALE line, however, the Spansion NOR I'm having here does not have this line.

My questions:

1. Is it possible for GPMC to interface with asynchronous NOR memory without this line?

2. If yes, am I suppose to ignore the configurations for ADV related register such as: GPMC_CONFIG3_i.ADVONTIME, GPMC_CONFIG3_i.ADVRDOFFTIME and GPMC_CONFIG3_i.etc?

3. And so, are the rest of the formulas still valid?

 

Thanks for any help!

 

  • tan jr said:
    1. Is it possible for GPMC to interface with asynchronous NOR memory without this line?

    Yes.  It requires more dedicated address pins to access the same amount of memory.  It's faster though because you don't need multiple phases to latch the address pins.

     

    tan jr said:
    2. If yes, am I suppose to ignore the configurations for ADV related register such as: GPMC_CONFIG3_i.ADVONTIME, GPMC_CONFIG3_i.ADVRDOFFTIME and GPMC_CONFIG3_i.etc?

    Those settings will not matter if the ADV pin is not actually connected to anything.

     

    tan jr said:
    3. And so, are the rest of the formulas still valid?

    What formulas?  In general I expect the timings to be better since you won't need to allow for multiple phases (i.e. no latching of addresses).