OMAPL138 DDR and Nandflash error

ben zhan

Other Parts Discussed in Thread: OMAPL138

hello,

I got a problem ,ti is very strange. when i test ddr2 independent in ccs3.3 , test passed. and I test nand flash in the internal RAM of DSP in ccs3.3 ,test passed too.

when I test DDR2 and Nandflash together, test failed. The data writed in the flash is not match with the data readed out. .

DSP run the example ok either in DDR2 RAM or in the internal RAM of DSP. I don't know how to solve the problem

can you give some advice, Thanks!

over 13 years ago

0 jc-ti over 13 years ago

TI__Mastermind 27585 points

What types of errors are you seeing? Are they single bit errors or completely corrupted data? Are you sure you are not placing the data in memory regions that might be getting overwritten?

Jeff

0 ben zhan over 13 years ago in reply to jc-ti

Intellectual 700 points

hi jc-ti:

Below is the error; The blue sector is the error filed. The DDR2 connected as fingure1.Nandflash conneted as fingure2.

Please help me analysize it ,thanks!

In addtion, I test DDR2 via the interal RAM of DSP ,the test is ok.

I test Nandflash via the interal RAM of DSP,the test is ok. the test program is same.

I use the DDR2 RAM to test nand flash ,The error occured as discribed. the DDR2 memory is 256MBytes, 16bits width, two 128MB 8bits DDR2 chips

CPU top view: OMAPL138AZWT $7-0BACV5W FR G1

figure1

figure2:

0 ben zhan over 13 years ago in reply to ben zhan

Intellectual 700 points

hi jc-ti,

Do you have any suggest! Thanks!

And now I can flash the AIS file and uboot to Nandflash in ccs3.3. I boot the board in nandflash mode, it can enter the uboot ,but the ENV can't be set.

I use tftp cmd to load the uImage to DDR2,and write it to Nandflash. It seems ok, but boot the kernel failed. In this occasion, I test the nandflash in ccs3.3 via DDR2 ,

the test failed again!

I have no idear now ,which path should I choose to analysize the errors.Thanks very much!

0 jc-ti over 13 years ago in reply to ben zhan

TI__Mastermind 27585 points

At this point you may want to check for shorts on your board. Theres no reason why the NAND would fail like that simply by moving the code to DDR, if you are sure the DDR is working properly.

Can you try booting U-boot from UART boot and TFTPing the kernel and file system to boot Linux? If you can successfully get to the Linux prompt, then we can rule out DDR issues.

Jeff

0 ben zhan over 13 years ago in reply to jc-ti

Intellectual 700 points

Hi jeff:

thanks for your reply. Now I test nandflash in DDR2,the test failed. I change the test program,the test passed,Information under below:

when use memcmp to compare data, the test failed!, But when I use for loop,the test passed,I do not understand.

uint32_t verifyFlashData(uint32_t verify_block, uint32_t verify_page, uint8_t *ram_start_addr, uint8_t print_data)
{
   uint32_t rtn = ERR_NO_ERROR;
   uint32_t i =0;
   //uint8_t *rx;

   //rx = &rx_buffer[0];
   rtn = NAND_readPage(verify_block, verify_page, rx_buffer);
   if (rtn != ERR_NO_ERROR)
   {
      printf("\terror while reading from nand flash during verify");
      return (rtn);
   }

   // print data if desired.
   if (print_data)
   {
      UTIL_printMem(verify_block, rx_buffer, MAX_BUFFER_SIZE, PRINT_HEADER);
   }
/*
   for(i = 0; i < MAX_BUFFER_SIZE;i++)
   {
      if( rx_buffer[i] != ram_start_addr[i])
   {
     printf("\rx_value:0x%x, tx_value:0x%x \n",rx_buffer[i],ram_start_addr[i]);
   printf("\rx_addr:0x%x, tx_addr:0x%x \n",&rx_buffer[i],&ram_start_addr[i]);
   }
   } */
   if (memcmp(rx_buffer, ram_start_addr, MAX_BUFFER_SIZE) != 0)
   {
      rtn = ERR_FLASH_VERIFY;
      printf("\tdata does not match!");
   }

   return (rtn);
}

2) 、When I change the DDR2 Freq. from 150MHz to 132MHz, I can use ccs3.3 flash writer to load AIS and uboot to Nandflash, I set the boot mode to Nandflash, booting uboot ok, but can't set env from uboot cmd line. when use tftp cmd to load uImage to DDR2 and bootm ,it tells me uImage CRC error. But this uImage is running ok on my last version board。 But test nandflash in ddr2 under ccs3.3, the test failed.

3)、I have some OMAPL138 chips ,they are version 2,375Mhz, I test the SD ok on my board, SO I want to boot uboot from SD, SO it needs D800K008 support, But I can't get AISgen tool which can support D800k008,Can you give me a latest AISgen tool,thanks!

0 jc-ti over 13 years ago in reply to ben zhan

TI__Mastermind 27585 points

1) Looks like the issue is the DDR related. Try running the attached DDR test to see if it reports any failures.

2) Again this indicated problems with the DDR. You've tried slowing the frequency down, but also try increasing all the timing parameters in the SDTIMER1/2 registers for the DDR to see if that affects anything.

Here is the code for memcmp. The difference may be 8 vs 32 bit reads, so try modifying your for loop to look more like the one below until you see the failures:

int memcmp(const void *cs, const void *ct, size_t n)

{

if (n)

{

const unsigned char *mem1 = (unsigned char *)cs;

const unsigned char *mem2 = (unsigned char *)ct;

int cp1, cp2;

while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n);

return cp1 - cp2;

}

return 0;

}

3) The latest AISgen tool is here: http://www.ti.com/dsp/docs/litabsmultiplefilelist.tsp?sectionId=3&tabId=409&literatureNumber=sprab41d&docCategoryId=1&familyId=1621

Jeff

ddr_edma_pattern_M1_M3.out

0 ben zhan over 13 years ago in reply to jc-ti

Intellectual 700 points

hi Jeff,

1) I Try running the attached DDR test to see if it reports any failures,there is no failures,,

2) I change my for loop code as you said, the test passed.

3) I tried to boot from uart2,but boot failed. I applied with steps under below:

first, I rebuilid my uboot, got uboot elf file.

second, I imported the uboot elf to AISgen tool for D800K008, got a u_boot_uart.bin.

Third,open the OMAPL138 Host tool V1.3 ,import the u_boot_uart.bin file ,start,reset and power on my board, some informations displayed,but boot failed :

0 Michael Shust over 13 years ago in reply to ben zhan

TI__Intellectual 1610 points

Based on this post, it appears there is an addressing issue. That pattern is pointing at an addressing issue. Things to check:

1) Make sure the DDR EMIF settings are correct and match the DDR devices used. DDR EMIF settings are the number one cause of DDR EMIF issues. Make sure to check things like bus turn around time. Errors in this setting may not show with a memory test but will cause havoc when trying to do real stuff.

2) Make sure the DDR device is connected properly. Check the schematic and check the netlist as well as the PCB layout.

3) Make sure you memory test tests addressability. Simple memory tests generally don't look for this and what could be happening is a write much later in time is corrupting the data in byte 08. It may be worth seeing if you can just do byte 0-F properly, then try the next 16 bytes.

4) It is possible there is some manufacturing problem causing a connection issue with the DDR.

5) The error pattern is very distinctive and is your smoking gun. Its very distinctive and odd and points away from a timing problem. A timing problem would affect all addresses.

6) It may be worth trying a constant pattern of zeros or F's to see if that works. If it does, then that is also an indication of an addressing problem.

7) Make sure ODT is actually grounded on the memory device.

-Mike

0 ben zhan over 13 years ago in reply to Michael Shust

Intellectual 700 points

hi Jeff,

I configure the ddr2 freq. at 132MHz, the boot information seems the booting ok, but I connect serial terminal at COM4, but can't not see anything, the uboot CMD line can't display.Is there any other problem.thanks!

(File IO): Read 193844 bytes from file C:\Documents and Settings\kcom\桌面\u-boot_uart.bin.
(Serial Port): Opening COM4 at 115200 baud...
(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse): Processing command 0: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 1: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 2: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 3: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 4: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 5: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 6: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 7: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 8: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 9: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 10: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 11: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 12: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 13: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 14: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 15: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 16: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 17: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 18: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 19: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 20: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 21: 0x5853590D.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Executing function...
(AIS Parse): Processing command 22: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 152056-Byte section to address 0xC1080000.
(AIS Parse): Processing command 23: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 31664-Byte section to address 0xC10A51F8.
(AIS Parse): Processing command 24: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 8008-Byte section to address 0xC10ACDA8.
(AIS Parse): Processing command 25: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 1596-Byte section to address 0xC10AECF0.
(AIS Parse): Processing command 26: 0x58535906.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Performing jump and close...
(AIS Parse): AIS complete. Jump to address 0xC1080000.
(AIS Parse): Waiting for DONE...
(AIS Parse): Boot completed successfully.
(Serial Port): Closing COM4.

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OMAPL138 DDR and Nandflash error