Part Number: Am64x-SK
Tool/software:
Hello TI,
I am trying to initialize the LPDDR4 ram on the am64x-sk. I've set the swithes into the following boot mode according to the documentation:
DEV BOOT MODE
AM64X-EVM
This mode is used in conjunction with the load_dmsc_hsfs.js script described here SOC Initialization Using CCS Scripting,
BOOTMODE [ 0 : 7 ] (SW2) = 1101 1110
BOOTMODE [ 8 : 15 ] (SW3) = 0000 0000
And I got this output:
MAIN_Cortex_R5_0_0: Device Type is HSFS MAIN_Cortex_R5_0_0: Running from R5 or A53 MAIN_Cortex_R5_0_0: Device Type is HSFS MAIN_Cortex_R5_0_0: Running from R5 or A53 MAIN_Cortex_R5_0_0: Running from R5 MAIN_Cortex_R5_0_0: DDR not initialized with R5 connect. Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR. ==== MAIN_Cortex_R5_0_0: --->>> LPDDR4 Initialization is in progress ... <<<--- MAIN_Cortex_R5_0_0: --->>> ECC Enabled <<<--- MAIN_Cortex_R5_0_0: --->>> After priming ECC memory, enable ECC_CK bit with hotmenu AM64 DDR Memory config --> Enable_TI_InlineECC_CK_During_Reads()<<<--- MAIN_Cortex_R5_0_0: --->>> DDR controller programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR controller programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PI programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PI programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Data Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Data Slice 0 programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Data Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Data Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Address Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Data Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Address Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Address Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Address slice 2 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY Address Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY programming in progress.. <<<--- MAIN_Cortex_R5_0_0: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<--- MAIN_Cortex_R5_0_0: --->>> DDR PHY programming completed... <<<--- MAIN_Cortex_R5_0_0: Running from R5 or A53 MAIN_Cortex_R5_0_0: Debugging enabled MAIN_Cortex_R5_0_0: Setting MAIN_PLL12_HSDIV0_CLKOUT_25MHz MAIN_Cortex_R5_0_0: hsdiv_value: 63 MAIN_Cortex_R5_0_0: HSDIV reset asserted MAIN_Cortex_R5_0_0: HSDIV divider value programmed. MAIN_Cortex_R5_0_0: HSDIV reset de-asserted MAIN_Cortex_R5_0_0: MAIN_PLL12_HSDIV0_CLKOUT set. MAIN_Cortex_R5_0_0: --->>> Set DDR PLL to 25MHz for FSP F0... <<<--- MAIN_Cortex_R5_0_0: Triggering start bit from PI... MAIN_Cortex_R5_0_0: --->>> DDR PI initialization started... <<<--- MAIN_Cortex_R5_0_0: Triggering start bit from CTL... MAIN_Cortex_R5_0_0: --->>> DDR CTL initialization started... <<<--- MAIN_Cortex_R5_0_0: --->>> Inside DDR_Change_freq_ack function ... <<<--- MAIN_Cortex_R5_0_0: --->>> Waiting for first frequency change request ... <<<---
It is waiting forever and not working.
