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AM6442: DDR Qualification DDR4

Alex Paul
Expert 5485 points
Part Number: AM6442


Tool/software:

Hi Experts,

We are planning the DDR4-verification with scope measurements. in order to place the input mask for write and reads correctly we need the level for Vref(DQ)_Write on the DRAM and Vref(DQ)_Read on the controller.

For Vref(DQ)_Write it would be enough to know the final Moderegisters that are sent to the DRAM.

How can we get this information?


For Vref(DQ)_Read we would expect we can get this information out of some registers on the controller.

How can we get this information?


Regards,
Alex

  • 0
    TI__Guru* 89485 points

    Alex, i'm looking into this and will get back to you

    Regards,

    James

  • 0 in reply to JJD
    TI__Expert 5485 points

    Thanks

  • 0 in reply to Alex Paul
    TI__Expert 5485 points

    Hi James,

    Is there any update on the inquiry mentioned above ? 

    Regards,
    Alex

  • 0 in reply to Alex Paul
    TI__Expert 5485 points

    Hi Team,
    Can you please provide some feedback on this ?

    Regards,

    Alex

  • +1 in reply to Alex Paul
    TI__Guru* 89485 points

    Hi Alex, sorry for the delayed response

    For DDR4, read VREFdq trained value can be found in PHY_PAD_VREF_CTRL_DQ_x (in PHY_90 and PHY_346 register, x represents the byte).  The parameter bit definition is:

    VREFSEL  phy_pad_vref_ctrl_dq_X[6:0]: VREF value
    EN phy_pad_vref_ctrl_dq_X[7]: 0=disable, 1 = enable
    MODE phy_pad_vref_ctrl_dq_X[11:8]: 0x4 = DDR4 Range 1, 0x5 = DDR4 Range 2

    You can obtain the VREF percentages with the following formulas:

    if (mode == 4): #DDR4 range 1
           vref_percent = ((vref_val * 0.297) + 53.9)/100
    elif (mode == 5): #DDR4 range 2
           vref_percent = ((vref_val * 0.297) + 39.7)/100

    Write VREFdq is not trained, but is a fixed value (our EVMs use 72.4%) which can be chosen using the DDR Register Configuration Tool.  The value can be be seen in the registers in  PI_MR6_DATA_F0_0 (in PI_303 register).  The bit definition is the same as defined in MR6 in the JEDEC spec or DDR datasheet.

    Regards,

    James