J784S4XEVM: C7x GPIO Interrupt path issue

Hi Charles,

Thanks for this in depth information, you have set up all the right things necessary to generate GPIO interrupts for C7x. 

Could you please provide the sciclient_defaultBoardcfg_rm.c with your modifications? Either the full file or as a diff with the original from the SDK.

Charles said:

I can trigger the interrupt (the code reach the callback function) by writing in the CLEC send reg.

Which register is that?

Thanks,

Neehar

Hi Neehar,

This is the diff for the sciclient_defaultBoardcfg_rm.c

--- sciclient_defaultBoardcfg_rm.c	2024-12-12 20:24:18.000000000 +0100
+++ sciclient_defaultBoardcfg_rm_new.c	2025-04-02 13:19:17.043496000 +0200
@@ -186,7 +186,7 @@
                 .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                 .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
             },
-            .resasg_entries_size = 468 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
+            .resasg_entries_size = 469 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
         },
     },
     .resasg_entries = {
@@ -251,6 +251,12 @@
             .host_id = TISCI_HOST_ID_A72_3,
         },
         {
+            .num_resource = 4,
+            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
+            .start_resource = 56,
+            .host_id = TISCI_HOST_ID_C7X_0_1,
+        },
+        {
             .num_resource = 16,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMPEVENT_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
             .start_resource = 0,

I wrote in the CLEC_EVT_CFG_ESR_j to trigger the interrupt from the CLEC which is the "Event send reg" in the "J784S4_Register_Public_20250116.xlsx".

Hi Charles,

Thanks for this information.

Can you confirm if sciclient is able to successfully register and configure the interrupt path?

Thanks,

Neehar

Hi Neehar,

The sciclient following functions work correctly :

- Sciclient_rmGetResourceRange

- Sciclient_rmIrqTranslateIrOutput

- Sciclient_rmIrqSet

And when I check the INTRTR router memory after Sciclient_rmIrqSet :

0xa000e4 = 0x10091

which is the GPIOMUX 56 address (it corresponds to the sciclient_defaultBoardcfg_rm.c).

The data means INT_ENABLE = 1 and MUX_CNTL = 145 (=bank interrupt : main GPIO0 bank 0).

Thanks

Charles

Hi Charles,

Thanks, I will look further and respond in a couple days due to low bandwidth.

Thanks,

Neehar

Hi Charles,

Sorry for the delay on this.

Charles said:

And when I check the INTRTR router memory after Sciclient_rmIrqSet :

0xa000e4 = 0x10091

Based on this register, is the input to GPIOMUX_INTRTR 145 and the output is 39? Is that correct?

Charles said:

0x600034 = 0x0

Is the interrupt status register never set when the interrupt is triggered?

Charles said:

0x79b81000 = 0x41100028

Is this the correct register for input 440 to the CLEC? The register mapping seems off from my calculations.

Thanks,

Neehar

Hi Neehar,

Neehar Sawant said:

Based on this register, is the input to GPIOMUX_INTRTR 145 and the output is 39? Is that correct?

based on the J784s4_Register_Public, the GPIOMUX_INTRTR_CFG_muxcntl register doesn't give the output :

But the output should be 44 cf PDK user guide 4.12.7.2.2. Interrupt Destination IDs (J784S4_DEV_COMPUTE_CLUSTER0_CLEC = 44)

Neehar Sawant said:

Is the interrupt status register never set when the interrupt is triggered?

It is when I press the SW3 button, but I clear it at init so that the next interrupt occures.

Neehar Sawant said:

Is this the correct register for input 440 to the CLEC? The register mapping seems off from my calculations.

This my code to config the CLEC event.

int32_t               ret;
CSL_ClecEventConfig   cfgClec;
CSL_CLEC_EVTRegs     *clecBaseAddr = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
eventId  = dst_host_irq; /* CLEC i/p Event Idx - Use Range from BoardCfg (value is 440)*/
intNum = 40

/* Configure CLEC for GPIO */
cfgClec.secureClaimEnable = FALSE;
cfgClec.evtSendEnable = TRUE;
cfgClec.rtMap = CSL_clecGetC7xRtmapCpuId();
cfgClec.extEvtNum = 0;
cfgClec.c7xEvtNum = intNum;

CSL_clecClearEvent(clecBaseAddr, eventId);
CSL_clecConfigEventLevel(clecBaseAddr, eventId, CLEC_EVT_CFG_MMR_HIGH_LEVEL);
ret = CSL_clecConfigEvent(clecBaseAddr, eventId, &cfgClec);

if (ret != CSL_PASS)
{
    PRINT_LOG("CSL_clecConfigEvent failed %d\n", ret);
}

based on the J784s4_Register_Public formula with the evt 440 (index 439)

1B7h*1 0000h+1 1000h+7800 0000h = 79B8 1000h

==> I got the same register addr using TI CSL function and by the calcul. The register mapping seems correct for me

Thanks,

Charles

Hi Charles,

Charles said:

based on the J784s4_Register_Public, the GPIOMUX_INTRTR_CFG_muxcntl register doesn't give the output :

The GPIOMUX_INTRTR has 180 total input interrupts and 64 total output interrupts. The GPIOMUX_INTRTR_CFG_muxcntl_j register will mux the input interrupt through the interrupt router to the output interrupt using this register. The value of j will describe the output interrupt, since j=0 to 63d, and bits [8:0] will enable the MUXCNTL for the input interrupt.

Based on your register value, I calculated the output is 39, however, can you double check and confirm?

Charles said:

It is when I press the SW3 button, but I clear it at init so that the next interrupt occures.

Okay thanks for confirming that, this is the correct, expected behavior.

Charles said:

based on the J784s4_Register_Public formula with the evt 440 (index 439)

1B7h*1 0000h+1 1000h+7800 0000h = 79B8 1000h

Yes I see now, sorry for the confusion as I was using 1B8h for 440.

And to confirm when you say C7x core 1 you mean c7x_1?

The register value seems correct for the CLEC as well to generate c7x event number 40 .

Charles said:

I wrote in the CLEC_EVT_CFG_ESR_j to trigger the interrupt from the CLEC which is the "Event send reg" in

What value did you write to this register when successfully interrupting the core?

Thanks,

Neehar

Neehar Sawant said:

The value of j will describe the output interrupt, since j=0 to 63d,

I agree that the value of j will determine the GPIOMUX_INTRTR output and then the CLEC input. 

I calculated that the GPIOMUX used is the 56

A0 00E4h = 38h*4h+4h+A0 0000h

with 38h = 56d

Based on this register, is the input to GPIOMUX_INTRTR 145 and the output is 56

this output is connected to the CLEC event 440.

Neehar Sawant said:

And to confirm when you say C7x core 1 you mean c7x_1?

That depends, it is the first core (called C7x_0 in CCS or C7x_1 at compilation) .

Neehar Sawant said:

What value did you write to this register when successfully interrupting the core?

I used "CSL_clecSendEvent" function but the register should ignores the value written.

Thanks,

Charles

Hi Charles,

Let me double check on this and get back to you.

Thanks,

Neehar

Hi Charles,

Thanks for raising this issue to me, I see and understand the issue with the event offset is incorrect. It does not correspond with the event offset required to map to the correct CLEC event as shown in the input event map below:

I will raise this issue in the GPIO driver to the development team.

Thanks,

Neehar